Integrated circuit and method of designing layout thereof

Patent metadata

Field	Value
Publication number	US-2016125117-A1
Application number	US-201514926128-A
Country	US
Kind code	A1
Filing date	Oct 29, 2015
Priority date	Oct 30, 2014
Publication date	May 5, 2016
Grant date	—

Abstract

A method of designing a layout of an integrated circuit (IC), which is implemented by a computer system or a processor, includes receiving input layout data, and performing a design rule check with regard to a plurality of patterns. The method includes, merging, from among a first pattern and a second pattern against the design rule, the first pattern with a third pattern connected to a same net as the first pattern, and generating output layout data.

First claim

What is claimed is:

1 . A computer implemented method for designing a layout of an integrated circuit (IC) which includes a plurality of patterns formed in a layer, the method comprising:
receiving input layout data comprising placement information regarding the plurality of patterns and coloring information in which each of the plurality of patterns has been matched to one of a plurality of masks; performing a design rule check with regard to the plurality of patterns; changing the placement information so that, with respect to a first pattern and a second pattern that violate the design rule, from among the plurality of patterns, the first pattern is merged with a third pattern connected to a same net as the first pattern to define a resulting pattern; and updating the coloring information so that the resulting pattern formed by merging the first and third patterns is matched to a mask corresponding to the third pattern.

2 . The method of claim 1 , wherein the first and second patterns correspond to a first mask, and the third pattern corresponds to a second mask different from the first mask, and the updating of the coloring information comprises updating the coloring information so that the resulting pattern formed by merging the first and third patterns is matched to the second mask.

3 . The method of claim 2 , wherein performing the design rule check comprises matching one of the first pattern and the second pattern to a mask different from the first mask from among the plurality of masks, and performing the design rule check with regard to patterns adjacent to the first and second patterns, the first pattern, and the second pattern.

4 . The method of claim 1 , wherein the IC comprises a plurality of regular cells each comprising at least one pin, and, in the placement information of the input layout data, the first to third patterns are respectively placed in pins comprised in different regular cells from among the plurality of regular cells.

5 . The method of claim 1 , wherein each of the plurality of patterns is a pattern formed in the layer to form a via, and the resulting pattern formed by merging the first and third patterns defines a pattern formed in the layer to form a bar-type via.

6 . The method of claim 1 , wherein the changing of the placement information comprises:
selecting the first and third patterns commonly connected to a power net of the IC and corresponding to the same mask; generating the resulting pattern obtained by merging the first and third patterns by extending each of the first and third patterns in the layer; and changing the placement information so that the layout comprises the resulting pattern formed by merging the first and third patterns.

7 . The method of claim 1 , wherein the design rule comprises:
a first rule defining a distance between two patterns corresponding to the same mask from among the plurality of patterns; and a second rule defining a distance between two patterns corresponding to different masks from among the plurality of patterns; wherein the distance defined by the first rule is greater than the distance defined by the second rule.

8 . The method of claim 1 further comprising generating output layout data comprising the changed placement information and the updated coloring information.

9 . A computer implemented method for designing a layout of an integrated circuit (IC) which includes a plurality of patterns formed in a layer, the method comprising:
receiving input layout data comprising placement information regarding the plurality of patterns; generating coloring information in which each of the plurality of patterns is matched to one of a plurality of masks; and generating output layout data comprising the coloring information; wherein generating of the coloring information comprises changing the placement information so that at least two patterns connected to a same net from among the plurality of patterns are merged and generating the coloring information so that the plurality of patterns and a resulting pattern formed by merging the at least two patterns are matched to one of the plurality of masks.

10 . The method of claim 9 , wherein changing of the placement information comprises:
selecting a first pattern and a second pattern commonly connected to a power net of the IC; generating the resulting pattern by merging the first and second patterns by extending each of the first and second patterns in the layer; and changing the placement information so that the layout comprises the resulting pattern formed by merging the first and second patterns.

11 . The method of claim 9 , wherein the at least two patterns are separated from each other by a predetermined distance or less.

12 . The method of claim 9 , wherein generating of the coloring information further comprises performing a design rule check with regard to the plurality of patterns, and the design rule comprises:
a first rule defining a distance between two patterns corresponding to the same mask from among the plurality of patterns; and a second rule defining a distance between two patterns corresponding to different masks from among the plurality of patterns.

13 . The method of claim 12 , wherein the distance defined by the first rule is greater than the distance defined by the second rule.

14 . The method of claim 9 , wherein the IC comprises a plurality of regular cells each comprising at least one pin, and, in the placement information of the input layout data, the at least two patterns are respectively placed in pins comprised in different regular cells from among the plurality of regular cells.

15 . The method of claim 9 , wherein each of the plurality of patterns is a pattern formed in the layer to form a via, and the resulting pattern formed by merging the at least two patterns defines a pattern formed in the layer to form a bar-type via.

16 . A computer implemented method for designing a layout of an integrated circuit (IC) which includes a plurality of patterns formed in a layer, the method comprising:
receiving input layout data comprising placement information regarding the plurality of patterns and coloring information in which each of the plurality of patterns has been matched to one of a plurality of masks; performing a design rule check with regard to the plurality of patterns to determine a first pattern and a second pattern that violate the design rule; changing the placement information so that the first pattern is merged with a third pattern to define a resulting pattern; updating the coloring information so that the resulting pattern formed by merging the first and third patterns is matched to a mask corresponding to the third pattern; and generating output layout data comprising the changed placement information and the updated coloring information.

17 . The method of claim 16 , wherein the first and second patterns correspond to a first mask, and the third pattern corresponds to a second mask different from the first mask, and the updating of the coloring information comprises updating the coloring information so that the resulting pattern formed by merging the first and third patterns is matched to the second mask.

18 . The method of claim 17 , wherein performing the design rule check comprises matching one of the first pattern and the second pattern to a mask different from the first mask from among the plurality of masks, and performing the design rule check with regard to patterns adjacent to the first and second patterns, the first pattern, and

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Jin-Tae
• Kim Ha-Young
• Seo Jae-Woo

Classifications

• G06F30/398 Primary

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title

• G06F30/392 Primary

  Floor-planning or layout, e.g. partitioning or placement · CPC title

• G06F17/5081

  Physics · mapped topic

• G06F17/5072 Primary

  Physics · mapped topic