Method of making a programmable cell and structure thereof
US-2016276355-A1 · Sep 22, 2016 · US
Two-bit read-only memory cell
US9147495B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9147495-B2 |
| Application number | US-201313778258-A |
| Country | US |
| Kind code | B2 |
| Filing date | Feb 27, 2013 |
| Priority date | Feb 27, 2013 |
| Publication date | Sep 29, 2015 |
| Grant date | Sep 29, 2015 |
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Abstract
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A read-only memory (ROM) cell has first and second transistors connected in series between a true bit line and a voltage reference (e.g., ground), and third and fourth transistors connected in series between a complement bit line and the voltage reference. The gates of the first and third transistors are connected to a first word line, and the gates of the second and fourth transistors are connected to a second word line. The ROM cell is programmed to store any possible combination of two bits of information by appropriately (i) connecting the node between the first and second transistors to either the true bit line, the complement bit line, or the voltage reference and (ii) connecting the node between the third and fourth transistors to either the true bit line, the complement bit line, or the voltage reference.
First claim
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What is claimed is: 1. An apparatus comprising a read-only memory cell comprising: first and second transistors connected at a first node and in series between a true bit line and a voltage reference; and third and fourth transistors connected at a second node and in series between a complement bit line and the voltage reference, wherein (i) gates of the first and third transistors are connected to a first word line and (ii) gates of the second and fourth transistors are connect…
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Physics · mapped topic
Physics · mapped topic
- G11C17/146Primary
Physics · mapped topic
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- What does patent US9147495B2 cover?
- A read-only memory (ROM) cell has first and second transistors connected in series between a true bit line and a voltage reference (e.g., ground), and third and fourth transistors connected in series between a complement bit line and the voltage reference. The gates of the first and third transistors are connected to a first word line, and the gates of the second and fourth transistors are conn…
- Who is the assignee on this patent?
- Lsi Corp, Avago Technologies General Ip
- What technology area does this patent fall under?
- Primary CPC classification G11C17/146. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Sep 29 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).