Bad bit register for memory

Patent metadata

Field	Value
Publication number	US-10394647-B2
Application number	US-201715630538-A
Country	US
Kind code	B2
Filing date	Jun 22, 2017
Priority date	Jun 22, 2017
Publication date	Aug 27, 2019
Grant date	Aug 27, 2019

Abstract

A memory device, a memory system, and corresponding methods are provided. The memory device includes a non-volatile random access memory. The non-volatile memory includes a suspect bit register configured to store addresses of bits that are determined to have had errors. The non-volatile memory further includes a bad bit register configured to store addresses of bits that both (i) appeared in the suspect bit register due to a first error and (ii) are determined to have had a second error. Hence, the memory device overcomes the aforementioned intrinsic write-error-rate by identifying the bad bits so they can be fused out, thus avoiding errors during use of the non-volatile random access memory.

First claim

What is claimed is:

1. A computer-implemented method, comprising:
configuring, in a non-volatile random access memory, a suspect bit register to store addresses of bits that are determined to have had errors; and
configuring, in the non-volatile random access memory, a bad bit register to store addresses of bits that both (i) appeared in the suspect bit register due to a first error and (ii) are determined to have had a second error occur after the addresses of the bits have already been stored in the suspect bit register.

2. The computer-implemented method of claim 1 , wherein the suspect bit register is configured to store the address of the bits that are determined to have had the errors subsequent to a burn-in process, and the method further comprises configuring a main register to identify bits determined to be bad during a burn-in process.

3. The computer-implemented method of claim 2 , further comprising configuring the main register and the bad bit register as a fuse bit register.

4. The computer-implemented method of claim 3 , wherein the main register and the bad bit register are comprised in the non-volatile random access memory.

5. The computer-implemented method of claim 2 , wherein the bits determined to be bad during the burn-in process correspond to electrical short circuit condition, and electrical open circuit conditions.

6. The computer-implemented method of claim 2 , wherein the main register is configured in the non-volatile random access memory.

7. The computer-implemented method of claim 2 , wherein the main register is configured in a one-time-programmable memory device.

8. The computer-implemented method of claim 1 , wherein the non-volatile random access memory is a Spin Torque Magnetoresistive Random Access Memory having magnetic tunnel junctions.

9. A computer-implemented method, comprising:
configuring (i) a bad bit register in a non-volatile memory to store addresses of words that include bits determined to have an unacceptable write-error rate such that the bad bit register stores the addresses that both (a) appeared in a suspect bit register in the non-volatile memory due to a first error and (b) are determined to have had a second error occur after the addresses of the bad bits have already been written into the suspect bit register, and (ii) the suspect bit register to identify addresses of bad bits to write into the bad bit register,
wherein, responsive to detecting an error using an error correction code, the method further includes searching for a match to an address of a bit relating to the error in the suspect bit register, and
wherein, responsive to a presence of the match, the method further includes removing the address of the bit relating to the error from the suspect bit register and writing the address of the bit relating to the error into the bad bit register.

Assignees

• IBM

Inventors

• Debrosse John K
• Worledge Daniel C

Classifications

• G11C2029/4402

  Internal storage of test result, quality data, chip identification, repair information · CPC title

• G11C2029/0403

  during or with feedback to manufacture · CPC title

• G11C29/789

  using non-volatile cells or latches · CPC title

• G11C29/52

  Protection of memory contents; Detection of errors in memory contents · CPC title

• G11C29/4401 Primary

  for self repair · CPC title