Oscillator with dynamic gain control

Patent metadata

Field	Value
Publication number	US-10389364-B2
Application number	US-201715471034-A
Country	US
Kind code	B2
Filing date	Mar 28, 2017
Priority date	Sep 15, 2015
Publication date	Aug 20, 2019
Grant date	Aug 20, 2019

Abstract

In one form, an oscillator includes an oscillator core circuit and a dynamic gain control circuit. The oscillator core circuit is for connection to a frequency reference element and provides a first clock signal using a negative gain element having a gain determined by a gain control signal. The dynamic gain control circuit is coupled to the oscillator core circuit for calibrating the gain control signal to a startup value based on oscillations reaching a first threshold during a startup state, and calibrating the gain control signal to a steady-state value based on oscillations falling to a second threshold after an end of the startup state and before entering a steady state. The first threshold is higher than the second threshold. The dynamic gain control circuit operates the oscillator core circuit during the steady state using the steady-state value.

First claim

What is claimed is:

1. An oscillator comprising:
an oscillator core circuit for connection to a frequency reference element for providing a first clock signal using a negative gain element having a gain determined by a gain control signal; and
an amplitude determination circuit for comparing an amplitude of oscillations of said first clock signal to a voltage threshold signal and activating an output in response to said amplitude exceeding said voltage threshold signal; and
a digital controller for calibrating said gain control signal during a steady-state calibration state by setting said voltage threshold signal to a steady-state threshold and said gain control signal to an initial steady-state value, and incrementally reducing said gain control signal from said initial steady-state value until said amplitude of oscillations falls below said voltage threshold, and operating said oscillator core circuit during a steady state using a calibrated steady-state value equal to a previous value of said gain control signal.

2. The oscillator of claim 1 , wherein said initial steady-state value is higher than a calibration target.

3. The oscillator of claim 1 , wherein said gain control signal is a current, wherein a gain of said negative gain element varies according to said current.

4. The oscillator of claim 1 , wherein said digital controller further stores said calibrated steady-state value in a flash memory, and in response to a completion of a startup state, said digital controller determines whether steady-state gain calibration has already been performed, and if said steady-state gain calibration has already been performed operates said oscillator core circuit during said steady state using said calibrated steady-state value stored in said flash memory.

5. The oscillator of claim 1 , wherein said amplitude determination circuit comprises a peak detector.

6. The oscillator of claim 1 , wherein said digital controller is operable to calibrate said gain control signal to a startup gain higher than said steady-state value for operation in a startup state prior to calibrating said steady-state value.

7. The oscillator of claim 6 , wherein said digital controller is operable to calibrate said gain control signal to a keep warm value lower than said steady-state value for operation in a keep warm state.

8. The oscillator of claim 1 , wherein said digital controller is operable to periodically re-calibrate said steady-state value during said steady-state to account for changes in an operating environment.

9. An oscillator comprising:
an oscillator core circuit for connection to a frequency reference element for providing a first clock signal using a negative gain element having a gain determined by a gain control signal; and
a dynamic gain control circuit coupled to said oscillator core circuit for calibrating said gain control signal to a startup value based on oscillations reaching a first threshold during a startup state, calibrating said gain control signal to a steady-state value based on oscillations falling to a second threshold after an end of said startup state and before entering a steady state, wherein said first threshold is higher than said second threshold, and operating said oscillator core circuit during said steady state using said steady-state value.

10. The oscillator of claim 9 , wherein said dynamic gain control circuit further stores said steady-state value so calibrated in a flash memory, and in response to an end of said startup state, said dynamic gain control circuit is operable to retrieve said steady-state value from said flash memory and to operate said oscillator core circuit during said steady state using said steady-state value.

11. The oscillator of claim 9 , wherein said dynamic gain control circuit is operable to periodically re-calibrate said steady-state value during said steady state to account for changes in an operating environment.

12. The oscillator of claim 9 , wherein said dynamic gain control circuit is operable to calibrate said gain control signal to a keep warm value based on oscillations falling to a third threshold during an entry into a keep warm state, said keep warm value lower than said steady-state value, and operating said oscillator core circuit during said keep warm state using said keep warm value.

13. The oscillator of claim 12 , wherein said dynamic gain control circuit periodically re-calibrates said keep warm value during said keep warm state to account for changes in an operating environment.

14. The oscillator of claim 13 , wherein said dynamic gain control circuit further stores said keep warm value so calibrated in a flash memory, and in response to an entry into said keep warm state, said dynamic gain control circuit is operable to retrieve said keep warm value from said flash memory and to operate said oscillator core circuit during said keep warm using said keep warm value.

15. A method comprising:
starting up an oscillator core circuit using a first gain as a gain control signal in a startup state;
detecting an end of said startup state using a dynamic gain control circuit, wherein said dynamic gain control circuit automatically detects an end of said startup state based on oscillations reaching a first threshold during said startup state;
calibrating said gain control signal to a steady-state value based on oscillations falling to a second threshold after an end of said startup state and before entering a steady state, wherein said first threshold is higher than said second threshold; and
operating said oscillator core circuit in said steady state using said steady-state value.

16. The method of claim 15 , further comprising:
storing said steady-state value so calibrated in a flash memory;
retrieving said steady-state value from said flash memory in response to an end of said startup state; and
operating said oscillator core circuit during said steady state using said steady-state value.

17. The method of claim 15 , further comprising:
periodically re-calibrating said steady-state value during said steady state to account for changes in an operating environment.

18. The method of claim 15 , further comprising:
calibrating said gain control signal to a keep warm value based on oscillations falling to a third threshold during an entry into a keep warm state, said keep warm value than steady-state value; and
operating said oscillator core circuit during said keep warm state using said keep warm value.

19. The method of claim 18 , further comprising:
periodically re-calibrating said keep warm value during said keep warm state to account for changes in an operating environment.

20. The method of claim 18 , further comprising:
storing said keep warm value so calibrated in a flash memory; and
in response to an entry into said keep warm state, retrieving said keep warm value from said flash memory; and
operating said oscillator core circuit during said keep warm using said keep warm value.

Assignees

• Silicon Lab Inc

Inventors

• Viegas Eduardo

Classifications

• H03G3/001

  Digital control of analog signals · CPC title

• H03B5/32

  being a piezoelectric resonator (selection of piezoelectric material H10N30/00) · CPC title

• H03L3/00 Primary

  Starting of generators · CPC title

• H03L5/00

  Automatic control of voltage, current, or power · CPC title

• H03B2200/0012

  Pierce oscillator · CPC title