Oscillator circuit

US2016308491A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2016308491-A1
Application numberUS-201415101646-A
CountryUS
Kind codeA1
Filing dateDec 10, 2014
Priority dateDec 16, 2013
Publication dateOct 20, 2016
Grant date

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

An oscillator circuit comprises a first, high-Q crystal oscillator and a second, low-Q oscillator arranged for kick-starting the crystal oscillator at switch-on by coupling the second oscillator to the first oscillator for a time period. The oscillator circuit is arranged to select the frequency of the second oscillator by placing the second oscillator in a phase locked loop with the first oscillator providing a reference frequency, and adjusting the frequency of the second oscillator towards the frequency of the first oscillator.

First claim

Opening claim text (preview).

1 . An oscillator circuit comprising: a first oscillator comprising a crystal and arranged to generate a first oscillation signal at a first frequency, wherein the first oscillator has a first Q-factor; a second oscillator arranged to generate a second oscillation signal at a second frequency, wherein the second oscillator has a second Q-factor lower than the first Q-factor; a phase detector arranged to generate a difference signal indicative of a phase difference between the first and second oscillation signals; a filter arranged to generate a frequency control signal by filtering the difference signal; a frequency control storage device arranged to store a value of the frequency control signal; a selector switch (SW 1 ) having selectable first and second selector states, wherein in the first selector state the selector switch (SW 1 ) is arranged to deliver to a frequency control input of the second oscillator the stored value of the frequency control signal, and in the second selector state the selector switch (SW 1 ) is arranged to deliver to the frequency control input of the second oscillator the frequency control signal generated by the filter whereby the second frequency is tuned towards the first frequency; a gating switch (SW 2 ) having selectable first and second gating states, wherein in the first gating state the gating switch (SW 2 ) is arranged to couple an output of the second oscillator to a terminal of the crystal and in the second gating state the gating switch (SW 2 ) is arranged to de-couple the output of the second oscillator from the terminal of the crystal; and a controller arranged to select the states of the selector switch (SW 1 ) and the gating switch (SW 2 ), to switch-on the first and second oscillators and to select the states of the selector switch (SW 1 ) and the gating switch (SW 2 ) such that for a first time period commencing when both of the first and second oscillators have been switched on, the selector switch (SW 1 ) has the first selector state and the gating switch (SW 2 ) has the first gating state, and for a second time period commencing at completion of the first time period, the gating switch (SW 2 ) has the second gating state, wherein a duration of the first time period is dependent on a difference between the first frequency and the second frequency and is within the range 1 2   F 1 - F 2  ± 25  % ,  where F 1 is the first frequency and F 2 is the second frequency. 2 . An oscillator circuit as claimed in claim 1 , wherein the controller is arranged to switch-on the second oscillator no later than switching-on the first oscillator. 3 . An oscillator circuit as claimed in claim 1 , wherein the oscillator circuit is arranged to perform frequency calibration during the second time period by the selector switch (SW 1 ) being arranged to have the second selector state and the frequency control storage device being arranged to update the stored value of the frequency control signal by storing a current value of the frequency control signal. 4 . An oscillator circuit as claimed in claim 3 , wherein the first and second oscillators are arranged to switch-off at completion of the storing of the current value of the frequency control signal. 5 . An oscillator circuit as claimed in claim 1 , comprising: an amplitude detector arranged to generate an amplitude signal indicative of an amplitude of the first oscillation signal; and wherein the controller is arranged to modify a/the duration of the first time period dependent on a time taken for the amplitude signal to reach a target amplitude during the second time period. 6 . An oscillator circuit as claimed in claim 5 , comprising: a target count storage device arranged to store a value of a target number of cycles of the second oscillation signal corresponding to the duration of the first time period, and a counter arranged to determine the completion of the first time period by counting the cycles of the second oscillation signal up to the target number during the first time period. 7 . An oscillator circuit as claimed in claim 6 , wherein: the counter is arranged to determine the time taken for the amplitude signal to reach the target amplitude during the second time period by counting the cycles of the second oscillation signal during the second time period until the amplitude signal reaches the target amplitude; wherein the controller is arranged to modify the duration of the first time period by modifying the stored value of the target number of cycles of the second oscillation signal dependent on the number of cycles of the second oscillation signal counted during the second time period time until the amplitude signal reaches the target amplitude. 8 . A wireless communication device comprising an oscillator circuit as claimed in claim 1 . 9 . A method of operating an oscillator circuit, the oscillator circuit comprising a first oscillator comprising a crystal and arranged to generate a first oscillation signal at a first frequency, wherein the first oscillator has a first Q-factor; and a second oscillator arranged to generate a second oscillation signal at a second frequency, wherein the second oscillator has a second Q-factor lower than the first Q-factor, the method comprising: switching on the first and second oscillators; generating a difference signal indicative of a phase difference between the first and second oscillation signals; generating a frequency control signal by filtering the difference signal; for a first time period commencing when both of the first and second oscillators have been switched on, delivering a stored value of a frequency control signal to a frequency control input of the second oscillator and delivering the second oscillation signal generated by the second oscillator to a terminal of the crystal; and for a second time period commencing with completion of the first time period, de-coupling the second oscillation signal from the terminal of the crystal and delivering the frequency control signal to the frequency control input of the second oscillator whereby the second frequency is tuned towards the first frequency, wherein a duration of the first time period is dependent on a difference between the first frequency and the second frequency and is within the range 1 2   F 1 - F 2  ± 25

Assignees

Inventors

Classifications

  • Starting of generators · CPC title

  • Starting, stopping or resetting the counter (counters with a base other than a power of two H03K23/48, H03K23/66) · CPC title

  • H03B5/06Primary

    Modifications of generator to ensure starting of oscillations · CPC title

  • being a piezoelectric resonator (selection of piezoelectric material H10N30/00) · CPC title

  • concerning mainly the controlled oscillator of the loop · CPC title

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What does patent US2016308491A1 cover?
An oscillator circuit comprises a first, high-Q crystal oscillator and a second, low-Q oscillator arranged for kick-starting the crystal oscillator at switch-on by coupling the second oscillator to the first oscillator for a time period. The oscillator circuit is arranged to select the frequency of the second oscillator by placing the second oscillator in a phase locked loop with the first osci…
Who is the assignee on this patent?
ERICSSON TELEFON AB L M (publ)
What technology area does this patent fall under?
Primary CPC classification H03B5/06. Mapped technology areas include Electricity.
When was this patent published?
Publication date Thu Oct 20 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).