Chamferless via structures

Patent metadata

Field	Value
Publication number	US-10388565-B2
Application number	US-201815982076-A
Country	US
Kind code	B2
Filing date	May 17, 2018
Priority date	Sep 2, 2015
Publication date	Aug 20, 2019
Grant date	Aug 20, 2019

Abstract

Chamferless via structures and methods of manufacture are provided. The method includes: forming at least one non-self-aligned via within at least dielectric material; plugging the at least one non-self-aligned via with material; forming a protective sacrificial mask over the material which plugs the at least one non-self-aligned via, after a recessing process; forming at least one trench within the dielectric material, with the protective sacrificial mask protecting the material during the trench formation; removing the protective sacrificial mask and the material within the at least one non-self-aligned via to form a wiring via; and filling the wiring via and the at least one trench with conductive material.

First claim

What is claimed:

1. A method comprising:
forming a non-self-aligned via within a dielectric material;
plugging the non-self-aligned via with a via fill material;
recessing the via fill material to below elements formed above the dielectric material;
forming a mask over the via fill material after the recessing step;
forming a trench within the dielectric material, with the mask protecting the non-self-aligned via and the via fill material;
removing the mask and the via fill material within the non-self-aligned via to form a wiring via; and
filling the wiring via and the trench with a conductive material.

2. The method of claim 1 , wherein the via fill material comprises an antireflective coating.

3. The method of claim 1 , wherein the via fill material comprises an optical planar layer.

4. The method of claim 1 , wherein the via fill material comprises a spin on material.

5. The method of claim 1 , wherein the via fill material comprises an ultra low-k dielectric material.

6. The method of claim 1 , wherein the dielectric material is an ultra low-k material.

7. The method of claim 1 , wherein the non-self-aligned via is further formed within an optical planarization layer above the dielectric material.

8. The method of claim 7 , wherein the non-self-aligned via is formed with several etch chemistries.

9. The method of claim 1 , wherein the mask selectively adheres to the via fill material.

10. The method of claim 9 , wherein the mask is Ruthinium.

11. The method of claim 1 , wherein the wiring via has vertical sidewalls at a sidewall angle greater than 85°.

12. A method comprising:
forming a non-self-aligned via within an optical planarization layer and an ultra low-k dielectric material;
plugging the non-self-aligned via with a via fill material;
recessing the via fill material;
removing the optical planar layer and an underlying etch stop material,
recessing the via fill material to below elements formed above the ultra low-k dielectric material;
forming a mask over the via fill material after the recessing the via fill material to below the elements;
forming a trench within the ultra low-k dielectric material, with the mask protecting the via fill material and the non-self-aligned via;
removing the mask and the via fill material within the non-self-aligned via to form a wiring via; and
filling the wiring via and the trench with a conductive material.

13. The method of claim 12 , wherein the via fill material comprises one of: an antireflective coating, an optical planar layer, a spin on material and an ultra low-k dielectric material.

14. The method of claim 12 , wherein the non-self-aligned via extends between the elements and through hardmask and etch stop materials to expose an underlying metal material.

15. The method of claim 14 , wherein the non-self-aligned via is formed with several etch chemistries.

16. The method of claim 14 , further comprising removing the elements, hardmask and etch stop materials, prior to filling the wiring via.

17. The method of claim 12 , wherein the mask selectively adheres to the via fill material.

18. The method of claim 12 , wherein the wiring via has vertical sidewalls with a constant angle in the ultra low-k dielectric material.

Assignees

• IBM
• Globalfoundries Inc

Inventors

• Lenhardt Mark L
• Mont Frank W
• Peethala Brown C
• Siddiqui Shariq
• Striss Jessica P
• Trickett Douglas M

Classifications

• H10W20/0693

  by forming self-aligned vias · CPC title

• H10P50/73

  using masks for insulating materials · CPC title

• H10W20/087

  involving multiple stacked pre-patterned masks · CPC title

• H10W20/085

  involving intermediate temporary filling with material · CPC title

• H10W20/082

  the openings being tapered via holes · CPC title