Chamferless via structures

Patent metadata

Field	Value
Publication number	US-9613862-B2
Application number	US-201514843109-A
Country	US
Kind code	B2
Filing date	Sep 2, 2015
Priority date	Sep 2, 2015
Publication date	Apr 4, 2017
Grant date	Apr 4, 2017

Abstract

Chamferless via structures and methods of manufacture are provided. The method includes: forming at least one self-aligned via within at least dielectric material; plugging the at least one self-aligned via with material; forming a protective sacrificial mask over the material which plugs the at least one self-aligned via, after a recessing process; forming at least one trench within the dielectric material, with the protective sacrificial mask protecting the material during the trench formation; removing the protective sacrificial mask and the material within the at least one self-aligned via to form a wiring via; and filling the wiring via and the at least one trench with conductive material.

First claim

What is claimed:

1. A method comprising:
forming at least one self-aligned via within at least a dielectric material;
plugging the at least one self-aligned via with a via fill material;
forming a protective sacrificial mask over the via fill material which plugs the at least one self-aligned via, after a recessing process in which the via fill material is recessed to below spacers formed above an ultra low-k dielectric material;
forming at least one trench within the dielectric material, with the protective sacrificial mask protecting the via fill material during the trench formation;
removing the protective sacrificial mask and the via fill material within the at least one self-aligned via to form a wiring via; and
filling the wiring via and the at least one trench with a conductive material.

2. The method of claim 1 , wherein the via fill material plugging the at least one self-aligned via comprises an antireflective coating.

3. The method of claim 1 , wherein the via fill material plugging the at least one self-aligned via comprises an optical planar layer.

4. The method of claim 1 , wherein the via fill material plugging the at least one self-aligned via comprises a spin on material.

5. The method of claim 1 , wherein the via fill material plugging the at least one self-aligned via comprises an ultra low-k dielectric material.

6. The method of claim 1 , wherein the dielectric material is an ultra low-k material.

7. The method of claim 1 , wherein the at least one self-aligned via is further formed within a planar optical layer above the dielectric material and extends between the spacers and through hardmask and etch stop materials to expose an underlying metal material.

8. The method of claim 7 , wherein the at least one self-aligned via is formed with several etch chemistries.

9. The method of claim 1 , wherein the protective sacrificial mask selectively adheres to the via fill material plugging the at least one self-aligned via, while leaving portions of the dielectric material exposed for the formation of the at least one trench.

10. The method of claim 9 , wherein the protective sacrificial mask is Ruthinium.

11. The method of claim 1 , wherein the wiring via is a chamferless wiring via with a sidewall angle greater than 85°.

12. A method comprising:
forming at least one self-aligned via within an optical planar layer and an ultra low-k dielectric material;
plugging the at least one self-aligned via with a via fill material selective to the ultra low-k dielectric material;
recessing the via fill material;
removing the optical planar layer and an underlying etch stop material to expose the ultra low-k dielectric material, wherein the removing step further recesses the via fill material to below spacers formed above the ultra low-k dielectric material;
forming a protective sacrificial mask over the via fill material which plugs the at least one self-aligned via;
forming at least one trench within the dielectric material, with the protective sacrificial mask protecting the via fill material during the forming of the at least one trench;
removing the protective sacrificial mask and the via fill material within the at least one self-aligned via to form a wiring via; and
filling the wiring via and the at least one trench with a conductive material.

13. The method of claim 12 , wherein the via fill material plugging the at least one self-aligned via comprises one of: an antireflective coating, an optical planar layer, a spin on material and an ultra low-k dielectric material.

14. The method of claim 12 , wherein the at least one self-aligned via extends between the spacers and through hardmask and etch stop materials to expose an underlying metal material.

15. The method of claim 14 , wherein the at least one self-aligned via is formed with several etch chemistries.

16. The method of claim 14 , further comprising removing the spacers, hardmask and etch stop materials, prior to filling the wiring via with the conductive material.

17. The method of claim 12 , wherein the protective sacrificial mask selectively adheres to the material plugging the at least one self-aligned via.

18. The method of claim 17 , wherein the protective sacrificial mask is Ruthinium.

19. The method of claim 12 , wherein the wiring via is a chamferless wiring via with a constant angle in the ultra low-k dielectric material.

Assignees

• IBM
• Globalfoundries Inc

Inventors

• Lenhardt Mark L
• Mont Frank W
• Peethala Brown C
• Siddiqui Shariq
• Striss Jessica P
• Trickett Douglas M

Classifications

• H10W20/0693

  by forming self-aligned vias · CPC title

• H10P50/73

  using masks for insulating materials · CPC title

• H10W20/087

  involving multiple stacked pre-patterned masks · CPC title

• H10W20/085

  involving intermediate temporary filling with material · CPC title

• H10W20/082

  the openings being tapered via holes · CPC title