Memory device and semiconductor device

Patent metadata

Field	Value
Publication number	US-9601178-B2
Application number	US-201213350086-A
Country	US
Kind code	B2
Filing date	Jan 13, 2012
Priority date	Jan 26, 2011
Publication date	Mar 21, 2017
Grant date	Mar 21, 2017

Abstract

To provide a memory device which operates at high speed or a memory device in which the frequency of refresh operations is reduced. In a cell array, a potential is supplied from a driver circuit to a wiring connected to a memory cell. The cell array is provided over the driver circuit. Each of memory cells included in the cell array includes a switching element, and a capacitor in which supply, holding, and discharge of electric charge are controlled by the switching element. Further, a channel formation region of the transistor used as the switching element includes a semiconductor whose band gap is wider than that of silicon and whose intrinsic carrier density is lower than that of silicon.

First claim

What is claimed is:

1. A memory device comprising:
a first driver circuit comprising a first transistor;
a second driver circuit comprising a second transistor; and
a cell array over the first driver circuit and the second driver circuit,
wherein the cell array comprises a first region comprising a first cell, a second region comprising a second cell, a third region comprising a third cell, and a fourth region comprising a fourth cell,
wherein the first cell, the second cell, the third cell, and the fourth cell each comprise a third transistor and a capacitor electrically connected to the third transistor,
wherein a gate of the third transistor of the first cell and a gate of the third transistor of the second cell are electrically connected to a first word line,
wherein a gate of the third transistor of the third cell and a gate of the third transistor of the fourth cell are electrically connected to a second word line,
wherein one of a source and a drain of the third transistor of the first cell and one of a source and a drain of the third transistor of the third cell are electrically connected to a first data line
wherein one of a source and a drain of the third transistor of the second cell and one of a source and a drain of the third transistor of the fourth cell are electrically connected to a second data line,
wherein an insulating film is over the first driver circuit and the second driver circuit and under the cell array,
wherein the insulating film comprises a first contact hole, a second contact hole, a third contact hole, and a fourth contact hole,
wherein the first contact hole is between the first region and the second region when seen from a top view,
wherein the second contact hole is between the third region and the fourth region when seen from the top view,
wherein the third contact hole is between the first region and the third region when seen from the top view,
wherein the fourth contact hole is between the second region and the fourth region when seen from the top view,
wherein a first wiring electrically connected to the first driver circuit is in contact with the first word line through the first contact hole,
wherein a second wiring electrically connected to the first driver circuit is in contact with the second word line through the second contact hole,
wherein a third wiring electrically connected to the second driver circuit is in contact with the first data line through the third contact hole,
wherein a fourth wiring electrically connected to the second driver circuit is in contact with the second data line through the fourth contact hole, and
wherein the third transistor comprises an oxide semiconductor film comprising a channel formation region.

2. The memory device according to claim 1 , wherein the oxide semiconductor film comprises In, Ga, and Zn.

3. The memory device according to claim 1 , wherein a hydrogen concentration of the oxide semiconductor film is 1×10 19 /cm 3 or less.

4. A semiconductor device comprising the memory device according to claim 1 .

5. The memory device according to claim 1 ,
wherein each of the first transistor and the second transistor comprises silicon in a channel formation region, and
wherein the oxide semiconductor film is provided over the channel formation region of the first transistor.

6. A memory device comprising:
a first driver circuit comprising a first transistor;
a second driver circuit comprising a second transistor; and
a cell array over the first driver circuit and the second driver circuit,
wherein the cell array comprises a first region comprising a first cell, a second region comprising a second cell, a third region comprising a third cell, and a fourth region comprising a fourth cell,
wherein the first cell, the second cell, the third cell, and the fourth cell each comprise a third transistor and a capacitor electrically connected to the third transistor,
wherein a gate of the third transistor of the first cell and a gate of the third transistor of the second cell are electrically connected to a first word line,
wherein a gate of the third transistor of the third cell and a gate of the third transistor of the fourth cell are electrically connected to a second word line,
wherein one of a source and a drain of the third transistor of the first cell and one of a source and a drain of the third transistor of the third cell are electrically connected to a first data line,
wherein one of a source and a drain of the third transistor of the second cell and one of a source and a drain of the third transistor of the fourth cell are electrically connected to a second data line,
wherein the first word line comprises a first power feeding point between the first region and the second region when seen from a top view,
wherein the second word line comprises a second power feeding point between the third region and the fourth region when seen from the top view,
wherein the first data line comprises a third power feeding point between the first region and the third region when seen from the top view,
wherein the second data line comprises a fourth power feeding point between the second region and the fourth region when seen from the top view,
wherein the first word line is supplied with a potential from the first driver circuit via the first power feeding point,
wherein the second word line is supplied with a potential from the first driver circuit via the second power feeding point,
wherein the first data line is supplied with a potential from the second driver circuit via the third power feeding point,
wherein the second data line is supplied with a potential from the second driver circuit via the fourth power feeding point, and
wherein the third transistor comprises an oxide semiconductor film comprising a channel formation region.

7. The memory device according to claim 6 , wherein the oxide semiconductor film comprises In, Ga, and Zn.

8. The memory device according to claim 6 , wherein a hydrogen concentration of the oxide semiconductor film is 1×10 19 /cm 3 or less.

9. A semiconductor device comprising the memory device according to claim 6 .

10. The memory device according to claim 6 ,
wherein each of the first transistor and the second transistor comprises silicon in a channel formation region, and
wherein the oxide semiconductor film is provided over the channel formation region of the first transistor.

Assignees

• Yamazaki Shunpei
• Koyama Jun
• Semiconductor Energy Lab

Inventors

• Yamazaki Shunpei
• Koyama Jun

Classifications

• G11C11/404 Primary

  with one charge-transfer gate, e.g. MOS transistor, per cell · CPC title

• G11C11/4085

  Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title

• H10D1/692

  Electrodes · CPC title

• H10D86/481

  integrated with passive devices, e.g. auxiliary capacitors · CPC title