Semiconductor device and driving method thereof

Patent metadata

Field	Value
Publication number	US-9443563-B2
Application number	US-201514678098-A
Country	US
Kind code	B2
Filing date	Apr 3, 2015
Priority date	Apr 29, 2011
Publication date	Sep 13, 2016
Grant date	Sep 13, 2016

Abstract

In a memory module including a memory cell array including memory cells arranged in matrix, each including a first transistor using an oxide semiconductor and a first capacitor; a reference cell including a p-channel third transistor, a second capacitor, and a second transistor using an oxide semiconductor; and a refresh timing detection circuit including a resistor and a comparator, wherein when a potential is supplied to the first capacitor through the first transistor, a potential is supplied to the second capacitor through the second transistor, wherein a drain current value of the third transistor is changed in accordance with the potential stored in the second capacitor, and wherein when the drain current value of the third transistor is higher than a given value, a refresh operation of the memory cell array and the reference cell are performed.

First claim

What is claimed is:

1. A semiconductor device comprising:
a memory cell comprising:
a first transistor; and
a first capacitor electrically connected to the first transistor, a reference memory cell comprising:
a second transistor, the second transistor being an n-type;
a second capacitor, one electrode of the second capacitor being electrically connected to one of a source and a drain of the second transistor; and
a third transistor, the third transistor being a p-type, and a gate of the third transistor being electrically connected to the one electrode of the second capacitor; and

a comparator being electrically connected to one of a source and a drain of the third transistor,
wherein the comparator is configured to generate a signal based on a change in a current of the third transistor,
wherein both the memory cell and the reference memory cell are configured to be refreshed based on the signal supplied from the comparator, and
wherein each of the first transistor and the second transistor comprises an oxide semiconductor layer.

2. The semiconductor device according to claim 1 , further comprising a resistor being electrically connected to the comparator and the one of the source and the drain of the third transistor.

3. The semiconductor device according to claim 1 , wherein a gate of the first transistor and a gate of the second transistor are electrically connected to each other.

4. The semiconductor device according to claim 1 , wherein a capacitance of the second capacitor is smaller than a capacitance of the first capacitor.

5. The semiconductor device according to claim 1 , wherein the oxide semiconductor layer comprises at least one of indium and zinc.

6. The semiconductor device according to claim 1 , wherein the third transistor is formed using a semiconductor substrate.

7. A semiconductor device comprising:
a memory cell comprising:
a first transistor; and
a first capacitor electrically connected to the first transistor,

a reference memory cell comprising:
a second transistor, the second transistor being an n-type;
a second capacitor, one electrode of the second capacitor being electrically connected to one of a source and a drain of the second transistor; and
a third transistor, the third transistor being a p-type, and a gate of the third transistor being electrically connected to the one electrode of the second capacitor; and

a comparator being electrically connected to one of a source and a drain of the third transistor,
wherein the comparator is configured to generate a signal based on a change in a current of the third transistor,
wherein both the memory cell and the reference memory cell are configured to be refreshed based on the signal supplied from the comparator, and
wherein each of the first transistor and the second transistor comprises:
an oxide semiconductor layer comprising a first region, a second region, and a channel formation region between the first region and the second region;

a gate insulating film over the oxide semiconductor layer;
a gate electrode over the gate insulating film;
a source electrode over and in contact with the first region; and
a drain electrode over and in contact with the second region.

8. The semiconductor device according to claim 7 , further comprising a resistor being electrically connected to the comparator and the one of the source and the drain of the third transistor.

9. The semiconductor device according to claim 7 , wherein a gate of the first transistor and a gate of the second transistor are electrically connected to each other.

10. The semiconductor device according to claim 7 , wherein a capacitance of the second capacitor is smaller than a capacitance of the first capacitor.

11. The semiconductor device according to claim 7 , wherein the oxide semiconductor layer comprises at least one of indium and zinc.

12. The semiconductor device according to claim 7 , wherein each of the first transistor and the second transistor further comprises a sidewall insulating film being in contact with a side surface of the gate electrode.

13. The semiconductor device according to claim 7 , wherein each of the first transistor and the second transistor further comprises a sidewall insulating film being in contact with a side surface of the gate electrode, the first region, and the second region.

14. The semiconductor device according to claim 7 , wherein each of the first transistor and the second transistor further comprises a sidewall insulating film being in contact with a side surface of the gate electrode and the channel formation region.

15. The semiconductor device according to claim 7 , wherein each of the first region and the second region comprises any one of phosphorus, nitrogen, and a rare gas.

16. The semiconductor device according to claim 7 , wherein the third transistor is formed using a semiconductor substrate.

Assignees

• Semiconductor Energy Lab

Inventors

• Atsumi Tomoaki
• Takewaki Yoshiya

Classifications

• G11C11/4091

  Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating · CPC title

• G11C5/10 Primary

  for interconnecting capacitors · CPC title

• G11C11/4099 Primary

  Dummy cell treatment; Reference voltage generators · CPC title

• G11C11/404

  with one charge-transfer gate, e.g. MOS transistor, per cell · CPC title

• G11C11/401 Primary

  forming cells needing refreshing or charge regeneration, i.e. dynamic cells · CPC title