Non-volatile storage system with compute engine to accelerate big data applications

Patent metadata

Field	Value
Publication number	US-10387303-B2
Application number	US-201715673143-A
Country	US
Kind code	B2
Filing date	Aug 9, 2017
Priority date	Aug 16, 2016
Publication date	Aug 20, 2019
Grant date	Aug 20, 2019

Abstract

A memory system (e.g. a solid state drive) includes one or more non-volatile memory die, a controller in communication with the memory die and a compute engine inside the memory system that is near the location of the data and can be used to perform common data manipulation operations.

First claim

What is claimed is:

1. A non-volatile storage system, comprising:
a controller; and
a memory die, the memory die includes:
a substrate;
a monolithic three dimensional non-volatile memory structure in which multiple memory levels are formed as part of the memory die above the substrate with no intervening substrates between the memory levels;
a compute engine configured to perform data manipulation operations on contents of data stored in the memory structure, and
an error correction engine, the compute engine and the error correction engine are implemented on a top surface of the substrate and below the memory structure of the memory die.

2. The non-volatile storage system of claim 1 , wherein:
the controller is configured to expose an application programming interface that can be used by a host application to perform data manipulation operations by the compute engine on contents of data stored in the memory structure; and
the controller is further configured to transfer commands between the controller and the compute engine.

3. The non-volatile storage system of claim 2 , wherein:
the error correction engine is configured to decode data stored in the memory die and present the decoded data to the compute engine for the compute engine to perform data manipulation operations on the decoded data.

4. The non-volatile storage system of claim 2 , wherein:
the compute engine is further configured to search a stream of data stored in the memory structure; and
the compute engine is further configured to sort a stream of data stored in the memory structure in an order specified by the host application.

5. The non-volatile storage system of claim 1 , wherein:
the compute engine is implemented by a plurality of non-volatile FPGA's that are configured by the non-volatile memory structure.

6. The non-volatile storage system of claim 1 , wherein:
the controller comprises a front end processor circuit and a back end processor circuit connected to the front end processor circuit, the memory die is connected to the back end processor circuit.

7. The non-volatile storage system of claim 6 , wherein:
the front end processor circuit is configured to implement a flash translation layer including performing memory management, logical to physical address translation, communication with a host, management of local volatile memory and management of operation of the non-volatile storage system.

8. The non-volatile storage system of claim 6 , wherein:
the back end processor circuit is configured to manage memory operations in the memory die at the request of the front end processor circuit, including programming, reading and erasing the memory die.

9. The non-volatile storage system of claim 6 , further comprising:
additional back end processor circuits; and
additional memory dies, each of the additional back end processor circuits communicate with the front end processor circuit and one or more of the additional memory dies; and
wherein the front end processor circuit is a master for the back end processor circuit and the additional back end processor circuits, the back end processor circuit is a slave circuit for the front end processor circuit, the additional back end processor circuits are slave circuits for the front end processor circuit.

10. The non-volatile storage system of claim 6 , wherein:
the controller includes a local volatile memory and an additional compute engine, the additional compute engine is connected to the local volatile memory and an interface between the back end processor circuit and the memory die.

11. The non-volatile storage system of claim 6 , wherein
the front end processor circuit includes an interface to a host, the compute engine is positioned on the storage system side of the interface to the host.

12. The non-volatile storage system of claim 1 , wherein:
the controller includes an additional compute engine.

13. The non-volatile storage system of claim 12 , wherein:
the additional compute engine is configured to execute a flash translation layer.

14. A non-volatile storage system, comprising:
a front end processor circuit configured to communicate with a host and perform logical to physical address translation;
a first back end processor circuit connected to the front end processor circuit;
a second back end processor circuit connected to the front end processor circuit;
a plurality of memory dies comprising a first set of memory dies connected to the first back end processor circuit via a first physical interface and a second set of memory dies connected to the second back end processor circuit via a second physical interface; and
a compute engine inside the non-volatile storage system and in communication with the front end processor circuit, the compute engine is configured to perform operations on data stored in the plurality of memory dies.

15. The non-volatile storage system of claim 14 , wherein:
the compute engine is positioned in the front end processor circuit.

16. The non-volatile storage system of claim 14 , wherein:
the compute engine is positioned in the first back end processor circuit.

17. The non-volatile storage system of claim 14 , wherein:
the compute engine is positioned in a memory die of the plurality of memory dies.

18. The non-volatile storage system of claim 14 , wherein:
the front end processor circuit includes an interface to a host, the compute engine is positioned on the storage system side of the interface to the host.

19. The non-volatile storage system of claim 14 , further comprising:
a local volatile memory,
wherein the compute engine is connected to the local volatile memory and an interface between the first back end processor circuit and the first set of memory dies, the front end processor circuit is connected to the local volatile memory, the front end processor circuit is configured to manage the local volatile memory, and the compute engine is in communication with the local volatile memory.

20. The non-volatile storage system of claim 14 , wherein:
the compute engine is connected between the first back end processor circuit and the front end processor circuit.

21. A non-volatile storage system, comprising:
a local volatile memory;
a front end processor circuit connected to the local volatile memory, the front end processor circuit includes a first processor, the front end processor circuit is configured to communicate with a host and manage the local volatile memory;
a first back end processor circuit connected to the front end processor circuit, the first back end processor circuit comprising a second processor separate from the first processor;
a second back end processor circuit connected to the front end processor circuit, the second back end processor circuit comprising a third processor separate from the first processor and the second processor;
non-volatile memory including a first subset of the non-volatile memory connected to the first back end processor circuit and a second subset of the non-volatile memory connected to the second back end processor circuit; and
a compute engine inside the non-volatile storage system and in communication with the local volatile memory and the front end processor circuit, the compute engine is configured to perform operations on data stored in the non-volatile memory using the local volatile memory.

22. The non-volatile storage system of claim 21 , wherein:
the compute engine is connected to the first back en

Assignees

• Western Digital Tech Inc

Inventors

• Mehra Pankaj
• Mohan Vidyabhushan
• Song Seung-Hwan
• Vucinic Dejan
• Sun Chao
• Qin Minghai
• De Arup

Classifications

• G06F3/061 Primary

  Improving I/O performance · CPC title

• G06F16/24561

  Intermediate data storage techniques for performance improvement · CPC title

• G06F3/0659

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

• G06F2212/7201

  Logical to physical mapping or translation of blocks or pages · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title