Semiconductor memory device providing analysis and correcting of soft data fail in stacked chips

Patent metadata

Field	Value
Publication number	US-2016357630-A1
Application number	US-201615143865-A
Country	US
Kind code	A1
Filing date	May 2, 2016
Priority date	Jun 5, 2015
Publication date	Dec 8, 2016
Grant date	—

Abstract

The semiconductor memory device includes first group dies including at least one buffer die, and second group dies including a plurality of memory dies stacked on the first group dies and conveying data through a plurality of TSV lines. Here, at least one of the plurality of memory dies includes a first type ECC circuit which generates transmission parity bits using transmission data to be transmitted to the first group die, and the buffer die includes a second type ECC circuit which corrects, when a transmission error occurs in the transmission data received through the plurality of TSV lines, the transmission error using the transmission parity bits and generates error-corrected data.

First claim

What is claimed is:

1 . A semiconductor memory device comprising:
first group dies comprising at least one buffer die; and second group dies comprising a plurality of memory dies, the plurality of memory dies stacked on the first group dies and conveying data through a plurality of through silicon via (TSV) lines, wherein at least one of the plurality of memory dies includes a first type error correction coding (ECC) circuit configured to generate transmission parity bits based on transmission data to the first group dies, and wherein the buffer die includes a second type ECC circuit configured to correct the transmission error using the transmission parity bits when a transmission error occurs in the transmission data received through the plurality of TSV lines.

2 . The semiconductor memory device of claim 1 , wherein the semiconductor memory device is a stacked memory device configured to convey the data and control signals through the plurality of TSVs lines.

3 . The semiconductor memory device of claim 1 , wherein the plurality of TSV lines are formed with through silicon vias.

4 . The semiconductor memory device of claim 1 , wherein the first type ECC circuit is configured to perform error correction on data outputted from the memory dies before sending the transmission data.

5 . The semiconductor memory device of claim 1 , wherein the transmission error occurring in the transmission data is a soft data fail which occurs due to noise of the plurality of TSV lines.

6 . The semiconductor memory device of claim 1 , wherein the semiconductor memory device is applied to a 3D chip structure or a 2.5D chip structure.

7 . The semiconductor memory device of claim 1 , wherein each of the plurality of memory dies comprises DRAM cells.

8 . The semiconductor memory device of claim 1 , wherein at least one of the plurality of memory dies comprises DRAM cells.

9 . The semiconductor memory device of claim 1 , wherein the semiconductor memory device is of a 3D chip structure to communicate with a host.

10 . The semiconductor memory device of claim 9 , wherein the host is connected with the buffer die through a data bus.

11 . A semiconductor memory device comprising:
a buffer die on a substrate; and a plurality of memory dies stacked on the buffer die and transmitting data through a plurality of through silicon via (TSV) lines, wherein each of the plurality of memory dies includes a first type error correction coding (ECC) circuit configured to generate transmission parity bits based on transmission data to be transmitted to the buffer die, and wherein the buffer die includes a second type ECC circuit configured to check whether a transmission error occurs in the transmission data received through the plurality of TSV lines and to correct the transmission error based on the transmission parity bits upon detecting transmission error.

12 . The semiconductor memory device of claim 11 , wherein the TSV lines are through electrodes implemented with through silicon vias.

13 . The semiconductor memory device of claim 12 , wherein the semiconductor memory device is a stacked memory device in which the butler die and the memory dies are stacked on the substrate and are connected through TSV lines.

14 . The semiconductor memory device of claim 11 , wherein the transmission error occurring in the transmission data comprises a soft data fail which occurs due to noise of the plurality of TSV lines.

15 . The semiconductor memory device of claim 11 , wherein the buffer die communicates with a host through a data bus in a 2.5D chip structure.

16 . A semiconductor memory device comprising:
first group dies comprising at least one buffer die; and second group dies comprising a plurality of memory dies which are stacked on the first group dies and conveying data through a plurality of through silicon via (TSV) lines, wherein at least one of the plurality of memory dies comprises a cell core error correction coding (ECC) circuit which generates transmission parity bits using transmission data to be transmitted to the first group dies, and wherein the butler die comprises a via ECC circuit which corrects, when a transmission error occurs in the transmission data received through the plurality of TSV lines, the transmission error using the transmission parity bits, generates error-corrected data, and sends the error-corrected data to a host.

17 . The semiconductor memory device of claim 16 , wherein the semiconductor memory device is a stacked memory device configured to conveys the data and control signals through the plurality of TSV lines.

18 . The semiconductor memory device of claim 16 , wherein the transmission error occurring in the transmission data is a soft data fail which occurs due to noise of the plurality of TSV lines.

19 . The semiconductor memory device of claim 16 , wherein each of the plurality of memory dies comprises DRAM cells.

20 . The semiconductor memory device of claim 16 , wherein the cell core ECC circuit is configured to perform error correction on data outputted from the memory dies before the transmission data is sent.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kang Donghun
• HA Kyoung-nam
• KIM Hyungdong
• JUNG Jun-Phil

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/401

  characterised by multiple insulating or insulated package substrates, interposers or RDLs · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W90/00

  Package configurations · CPC title