Three-dimensional memory device having a buried source line extending to scribe line and method of making thereof

Patent metadata

Field	Value
Publication number	US-10381373-B2
Application number	US-201715720306-A
Country	US
Kind code	B2
Filing date	Sep 29, 2017
Priority date	Jun 16, 2017
Publication date	Aug 13, 2019
Grant date	Aug 13, 2019

Abstract

A method of forming a three-dimensional memory device includes forming at the least one lower level dielectric layer over a semiconductor substrate, forming a buried source line over the least one lower level dielectric layer and over the semiconductor substrate, such that the buried source line is electrically connected to the semiconductor substrate, forming an alternating stack of insulating layers and sacrificial material layers over the buried source line, such that the sacrificial material layers are subsequently replaced with, electrically conductive layers, forming memory openings through the alternating stack by etching through the alternating stack after the buried source line is electrically connected to the semiconductor substrate, and forming memory stack structures in the memory openings. Each memory stack structure includes a vertical semiconductor channel electrically connected to the buried source line and a memory film laterally surrounding the vertical semiconductor channel.

First claim

What is claimed is:

1. A method of forming a three-dimensional memory device, comprising:
forming at least one lower level dielectric layer over a semiconductor substrate;
forming an opening in the at least one lower level dielectric layer located in a scribe region to expose the semiconductor substrate;
forming a buried source line over the least one lower level dielectric layer and over the at semiconductor substrate, such that the buried source line is electrically connected to the semiconductor substrate, wherein the buried source line is formed over the at least one lower level dielectric layer and in the opening, such that an electrically conductive connection is formed in the opening to electrically connect the buried source line to the semiconductor substrate in the scribe region;
forming an alternating stack of insulating layers and sacrificial material layers over the buried source line, wherein the sacrificial material layers are subsequently replaced with electrically conductive layers;
forming memory openings through the alternating stack by etching through the alternating stack after the buried source line is electrically connected to the semiconductor substrate; and
forming memory stack structures in the memory openings, wherein each memory stack structure includes a vertical semiconductor channel electrically connected to the buried source line and a memory film laterally surrounding the vertical semiconductor channel.

2. The method of claim 1 , further comprising dicing the semiconductor substrate into chips through the scribe region after the step of forming the memory stack structures, wherein the dicing cuts off the electrically conductive connection between the buried source line and the semiconductor substrate.

3. The method of claim 1 , wherein:
the buried source line comprises downward-protruding portions that are electrically shorted to an upper portion of the semiconductor substrate;
the memory openings are formed using an anisotropic etch process; and
the downward-protruding portions conduct electrical charge between the buried source line and the semiconductor substrate during the anisotropic etch process.

4. The method of claim 1 , further comprising at least one source strap structure contacting a respective subset of the semiconductor channels of the memory stack structures.

5. A method of forming a three-dimensional memory device, comprising:
forming field effect transistors on a semiconductor substrate;
forming at least one lower level dielectric layer and lower metal interconnect structures over the field effect transistors and over the semiconductor substrate;
forming a buried source line over the at least one lower level dielectric layer and over the semiconductor substrate, such that the buried source line is electrically connected to the semiconductor substrate, wherein the buried source line comprises downward-protruding portions that are electrically connected to an upper portion of the semiconductor substrate;
forming an alternating stack of insulating layers and sacrificial material layers over the buried source line, wherein the sacrificial material layers are subsequently replaced with electrically conductive layers;
forming memory openings through the alternating stack by etching through the alternating stack after the buried source line is electrically connected to the semiconductor substrate;
forming memory stack structures in the memory openings, wherein each memory stack structure includes a vertical semiconductor channel electrically connected to the buried source line and a memory film laterally surrounding the vertical semiconductor channel; and
electrically isolating a portion of the buried source line that underlies the memory stack structures from the downward-protruding portions by laterally dividing the buried source line in a region between the memory stack structures and the downward-protruding portions,
wherein:
the memory openings are formed using an anisotropic etch process; and
the downward-protruding portions conduct electrical charge between the buried source line and the semiconductor substrate during the anisotropic etch process.

6. The method of claim 5 , wherein:
the buried source line comprises a semiconductor material layer overlying a metallic layer;
the openings extend into an upper portion of the semiconductor material layer; and
the memory film comprises from outside to inside a charge trapping layer comprising a material that traps electrical charge and a tunneling dielectric layer that contacts an outer sidewall of the vertical semiconductor channel.

7. The method of claim 6 , wherein the downward-protruding portions comprise an annular ring structure that is located in proximity to a bevel region of the semiconductor substrate and laterally encloses each chip region on the substrate.

8. The method of claim 6 , wherein the downward-protruding portions comprise a rectangular ring structure that is located in a scribe region that laterally surrounds a chip region.

9. The method of claim 6 , further comprising forming via cavities into an uppermost layer of the at least one lower level dielectric layer only within a scribe region while not forming any via cavity within a chip region, wherein the downward-protruding portions are formed in the via cavities.

10. The method of claim 9 , wherein:
the lower metal interconnect structures comprise scribe region metal interconnect structures that are electrically shorted to portions of the semiconductor substrate and are formed in the scribe region; and
the downward-protruding portions of the buried source line are formed on the scribe region metal interconnect structures.

11. The method of claim 5 , further comprising:
patterning the alternating stack to form stepped surfaces, wherein an overlying spacer material layer has a lesser lateral extent than an underlying spacer material layer within a region of the stepped surfaces;
forming a retro-stepped dielectric material portion on the stepped surfaces, wherein the retro-stepped dielectric material portion overlies the at least one lower level dielectric layer;
forming word line contact via structures on a top surface of a respective one of the electrically conductive layers within the region of the stepped surfaces; and
forming through-memory-level contact via structures through the retro-stepped dielectric material portion and on a subset of the lower metal interconnect structures.

12. The method of claim 11 , further comprising:
forming at least one upper level dielectric layer over the alternating stack; and
forming upper level metal interconnect structures in the at least one upper level dielectric layer, wherein the through-memory-level contact via structures are electrically shorted to a respective one of the upper level metal interconnect structures and a respective one of the lower metal interconnect structures.

13. The method of claim 5 , wherein the three-dimensional memory device includes an array of NAND strings that are located in a respective region of the alternating stack.

14. The method of claim 13 , wherein:
the semiconductor substrate comprises a silicon substrate;
the field effect transistors comprise a driver circuit for the array of NAND strings; and
the array of NAND strings comprises:
the vertical semiconductor channels, wherein at least one end portion of each of the vertical semiconductor channels extends substantially perpendicular to a top surface of the semiconductor substrate;
a plurality of charge storage elements, each charge storage element located adjacent to a respective one of the vertical sem

Assignees

• Sandisk Technologies Llc

Inventors

• Okizumi Yasuchika
• Hirayama Michiru
• Norizuki Naoto
• Shimizu Satoshi
• Kasagi Yasuo
• Naruse Kimiaki

Classifications

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• H01L27/11582 Primary

  Electricity · mapped topic

• H01L27/11573

  Electricity · mapped topic

• H01L27/11565

  Electricity · mapped topic

• H01L27/0688

  Electricity · mapped topic