Semiconductor packages and methods for forming semiconductor package

Patent metadata

Field	Value
Publication number	US-10381280-B2
Application number	US-201715477170-A
Country	US
Kind code	B2
Filing date	Apr 3, 2017
Priority date	Oct 10, 2013
Publication date	Aug 13, 2019
Grant date	Aug 13, 2019

Abstract

Semiconductor packages and methods for forming a semiconductor package are presented. The semiconductor package includes a package substrate having a die region on a first surface thereof. The package includes a die having a sensing element. The die is disposed in the die region and is electrically coupled to contact pads disposed on the first surface of the package substrate by insulated wire bonds. A cap is disposed over the first surface of the package substrate. The cap and the first surface of the package substrate define an inner cavity which accommodates the die and the insulated wire bonds. The insulated wire bonds are directly exposed to an environment through at least one access port of the package.

First claim

What is claimed is:

1. A semiconductor package comprising:
a package substrate, wherein the package substrate comprises a top substrate surface and a bottom substrate surface, wherein the package substrate is defined with a die region and a non-die region surrounding the die region;
conductive traces disposed within the package substrate;
via contacts disposed within the package substrate and below the conductive traces;
a die disposed on the top substrate surface and in the die region, wherein the die comprises a micro-electro-mechanical system (MEMS) sensor with a sensing element disposed on a surface of the die;
a cap disposed over the top substrate surface, wherein the cap and the top substrate surface define an inner cavity over the die, wherein the inner cavity comprises an empty void over and surrounding the die;
at least one access port in communication with an external environment outside of the semiconductor package, wherein the access port exposes the sensing element to the external environment through the empty void of the inner cavity; and
package contacts disposed on the bottom substrate surface, wherein the via contacts in the package substrate couple the package contacts to the conductive traces.

2. The semiconductor package of claim 1 wherein:
the cap comprises a top portion and sidewalls; and
the access port extends through inner and outer surfaces of the top portion of the cap, wherein the access port is disposed directly above the sensing element of the die.

3. The semiconductor package of claim 1 wherein:
the top substrate surface comprises contact pads in the inner cavity between the die and the cap;
the die comprises die pads on the surface of the die; and
insulated wire bonds electrically coupling the die pads to the contact pads, wherein each of the insulated wire bonds comprises a conductive wire and a dielectric coating surrounding the conductive wire.

4. The semiconductor package of claim 3 further comprising:
a stud bump disposed on each die pad, wherein a first end of each of the insulated wire bonds is coupled to the contact pad by a ball bond and a second end of each of the insulated wire bonds is coupled to the stud bump by a stitch bond; and
a protective layer covering the first and second ends of each of the insulated wire bonds, wherein the protective layer covers the ball bond and the stitch bond.

5. The semiconductor package of claim 1 wherein the package substrate comprises a printed circuit board substrate.

6. The semiconductor package of claim 1 wherein:
the cap comprises a top portion and sidewalls; and
the access port extends through inner and outer surfaces of the sidewalls of the cap.

7. The semiconductor package of claim 6 comprising:
a dielectric sealing ring disposed on the die and surrounding the sensing element;
a semiconductor lid is attached to a top surface of the dielectric sealing ring;
wherein the semiconductor lid, the dielectric sealing ring and the die define a sensing cavity which accommodates the sensing element; and
wherein the sensing cavity is disposed within the inner cavity, the access port of the cap exposes the sensing cavity to the external environment through the empty void of the inner cavity.

8. The semiconductor package of claim 1 comprising a non-conductive stiffener disposed within the package substrate, wherein the non-conductive stiffener is disposed below the conductive traces.

9. The semiconductor package of claim 8 wherein the package substrate comprises a first dielectric layer, wherein the first dielectric layer is disposed between the conductive traces and isolates one conductive trace from another conductive trace, wherein the stiffener is disposed below the first dielectric layer.

10. The semiconductor package of claim 9 wherein the package substrate comprises a second dielectric layer, wherein the second dielectric layer is disposed between the via contacts and isolates one via contact from another via contact, wherein at least one of the via contacts extends beyond a bottom of the second dielectric layer.

11. The semiconductor package of claim 10 wherein the package substrate comprises a patterned leadframe, wherein the patterned leadframe defines the conductive traces and the via contacts, wherein the first and second dielectric layers of the package substrate is disposed within recesses of the patterned leadframe.

12. A semiconductor package comprising:
a package substrate, wherein the package substrate comprises a top substrate surface and a bottom substrate surface, wherein the package substrate is defined with a die region and a non-die region surrounding the die region;
conductive traces disposed within the package substrate;
via contacts disposed within the package substrate and below the conductive traces;
a die disposed on the top substrate surface and in the die region, wherein the die comprises die pads and a sensing element disposed on a surface of the die, wherein insulated wire bonds electrically couple the die pads to contact pads disposed on the top substrate surface, wherein each of the insulated wire bonds comprises a conductive wire and a dielectric coating surrounding the conductive wire;
a cap having a top portion and sidewalls disposed over the top substrate surface, wherein the cap and the top substrate surface define an inner cavity which accommodates the die and the insulated wire bonds, wherein the top portion of the cap comprises a transparent material and the sidewalls of the cap comprise a dielectric material;
at least one access port in communication with an external environment outside of the semiconductor package, wherein the access port exposes the die to the external environment; and
package contacts disposed on the bottom substrate surface, wherein the via contacts in the package substrate couple the package contacts to the conductive traces.

13. A semiconductor package comprising:
a package substrate, wherein the package substrate comprises a top substrate surface and a bottom substrate surface, wherein the package substrate is defined with a die region and a non-die region surrounding the die region;
a die having a bottom die surface attached to the die region; and
a cap which includes a top and sides, wherein the sides of the cap are attached to the non-die region of the top substrate surface, wherein an inner surface of the cap creates an inner cavity, wherein the inner cavity comprises an empty void over and surrounding the die.

14. The semiconductor package of claim 13 wherein:
the top substrate surface of the package substrate comprises contact pads in the cavity between the die and the cap;
the die comprises die pads on a top surface of the die; and
wire bonds electrically coupling the die pads to the contact pads.

15. The semiconductor package of claim 14 wherein:
a top surface of the package substrate includes conductive traces on the top substrate surface coupled to the contact pads; and
via contacts in the package substrate couple package contacts on a bottom surface of the package substrate to the conductive traces.

16. The semiconductor package of claim 14 wherein the wire bonds comprise insulated wire bonds, the insulated wire bonds each comprises a conductive wire and a dielectric coating surrounding the conductive wire.

17. The semiconductor package of claim 16 comprises:
stud bumps disposed on the die pads; and
first ends of the insulated wire bonds are coupled to the contact pads by ball bonds and second ends of the insulated wire bonds are coupled to the stud bumps by stit

Assignees

• Utac Headquarters Pte Ltd

Inventors

• Suthiwongsunthorn Nathapong
• Beleran John Ducyao
• Pedron Jr Serafin Padilla

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W72/07554

  changes in dispositions · CPC title

• H10W72/5525

  comprising copper [Cu] · CPC title