Apparatuses for integrating arithmetic with logic operations

Patent metadata

Field	Value
Publication number	US-10379852-B2
Application number	US-201715685332-A
Country	US
Kind code	B2
Filing date	Aug 24, 2017
Priority date	Jun 27, 2017
Publication date	Aug 13, 2019
Grant date	Aug 13, 2019

Abstract

An apparatus for integrating arithmetic with logic operations contains at least a calculation device and a post-logic unit. The calculation device calculates source data to generate and output first destination data. The post-logic unit, coupled to the calculation device, performs a comparison operation for comparing the first destination data with 0 and outputs a comparison result.

First claim

What is claimed is:

1. An apparatus for integrating arithmetic with logic operations, comprising:
a calculation device, calculating source data to generate and output first destination data; and
a post-logic unit, coupled to the calculation device, performing a comparison operation for comparing the first destination data with 0, and outputting a comparison result;
wherein the post-logic unit is coupled to the calculation device via a delay circuit,
wherein the calculation device generates and outputs the first destination data at one cycle,
wherein the post-logic unit performs the comparison operation for comparing the first destination data with 0 and outputs the comparison result at the next cycle.

2. The apparatus of claim 1 , wherein the first destination data is a floating-point value and not undergone a normalization.

3. The apparatus of claim 1 , comprising:
a normalization unit, coupled to the calculation device via the delay circuit, normalizing the first destination data to generate second destination data,
wherein the normalization unit normalizes the first destination data to generate the second destination data at the next cycle.

4. The apparatus of claim 1 , wherein the comparison operation comprises one of the following determinations:
whether the first destination data is greater than 0;
whether the first destination data equals 0;
whether the first destination data equals or is greater than 0;
whether the first destination data is less than 0;
whether the first destination data does not equal 0; and
whether the first destination data is less than or equals 0.

5. The apparatus of claim 4 , wherein the post-logic unit comprises a comparator obtaining a signal from an ID (Instruction Decode) unit and performing one of the determinations according to the comparison Opcode.

6. The apparatus of claim 1 , wherein the calculation device performs a calculation:
dest= Src 0× Src 1+ Src 2,

Src0, Src1 and Src2 represent the source data of three source memories, and dest represents the first destination data.

7. The apparatus of claim 6 , comprising:
a normalization unit, coupled to the calculation device, normalizing the first destination data to generate the second destination data of a first type when receiving the signal indicating an output of first-type data, and normalizing the first destination data to generate the second destination data of a second type when receiving the signal indicating an output of second-type data.

8. The apparatus of claim 7 , wherein the second destination data of the first type is 24-bit floating-point value, and the second destination data of the second type is 32-bit floating-point value.

9. The apparatus of claim 7 , wherein the normalization unit comprises:
a shifter;
an adder;
a comparator, coupled to the shifter and the adder, wherein the comparator, the shifter and the adder form a loop for performing a normalization of a floating-point value; and
a merger, coupled to the shifter and the adder, combining a sign bit, a mantissa output from the shifter and an exponent output from the adder to generate the second destination data.

10. The apparatus of claim 9 , wherein the shifter drops 7 bits from a mantissa of 34 bits of the first destination data and the adder drops 1 bit from an exponent of 10 bits of the first destination data when receiving the signal indicating an output of first-type data.

11. The apparatus of claim 10 , wherein the comparator repeatedly operates until the MSB (Most Significant Bit) of a output from the shifter is 1,
wherein, in each iteration, when the MSB of the output of the shifter is not 1, the comparator directs the shifter to left-shift the mantissa of the first destination data by one bit and directs the adder to add −1 to the exponent of the first destination data.

Assignees

• Via Alliance Semiconductor Co Ltd

Inventors

• Zhang Huaisheng
• Liang Dacheng
• Chen Boming
• Bian Renyu

Classifications

• G06F9/30189

  according to execution mode, e.g. mode flag · CPC title

• G06F9/30029

  Logical and Boolean instructions, e.g. XOR, NOT · CPC title

• G06F9/30014 Primary

  with variable precision · CPC title

• G06F7/483

  Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers {(G06F7/4806, G06F7/4824, G06F7/49, G06F7/491, G06F7/544 take precedence)} · CPC title

• G06T1/20

  Processor architectures; Processor configuration, e.g. pipelining · CPC title