Apparatuses and methods for concurrently accessing different memory planes of a memory

Patent metadata

Field	Value
Publication number	US-2018366167-A1
Application number	US-201816109628-A
Country	US
Kind code	A1
Filing date	Aug 22, 2018
Priority date	Aug 15, 2014
Publication date	Dec 20, 2018
Grant date	—

Abstract

Apparatuses and methods for performing concurrent memory access operations for different memory planes are disclosed herein. An example apparatus may include a memory array having a plurality of memory planes. Each of the plurality of memory planes comprises a plurality of memory cells. The apparatus may further include a controller configured to receive a group of memory command and address pairs. Each memory command and address pair of the group of memory command and address pairs may be associated with a respective memory plane of the plurality of memory planes. The internal controller may be configured to concurrently perform memory access operations associated with each memory command and address pair of the group of memory command and address pairs regardless of page types associated with the pairs of the group (e.g., even if two or more of the memory command and address pairs may be associated with different page types).

First claim

What is claimed is:

1 . An apparatus, comprising:
a plurality of memory planes, each memory plane of the plurality of memory planes including a plurality of memory cells; a plurality of power circuits, each power circuit of the plurality of power circuits associated with a respective one of the plurality of memory planes, each power circuit of the plurality of power circuits configured to provide voltages to a respective memory plane of the plurality of memory planes; and a controller coupled to the plurality of power circuits, the controller configured to configure the plurality of power circuits for concurrent memory access operations, the controller further configured to concurrently access the plurality of memory planes after configuring each of the plurality of power circuits during the concurrent memory access operations.

2 . The apparatus of claim 1 , further comprising:
a plurality of driver circuits, wherein each power circuit of the plurality of power circuits is coupled to a respective one of the plurality of driver circuits, and wherein a driver circuit of the plurality of driver circuits is configured to provide voltages to access lines of a respective memory plane of the plurality of memory planes.

3 . The apparatus of claim 2 , wherein the power control controller is further configured to concurrently and independently configure the plurality of driver circuits for the concurrent memory access operations.

4 . The apparatus of claim 1 , wherein the controller further comprises a power control circuit configured to concurrently and independently configure the plurality of power circuits for the concurrent memory operations.

5 . An apparatus, comprising:
a memory array comprising a plurality of memory planes, wherein each of the plurality of memory planes comprises a plurality of memory cells; a plurality of power circuits; and a controller configured to concurrently perform memory access operations on each memory plane of the plurality of memory planes for a corresponding memory command and address pair, wherein the controller comprises a power control circuit configured to serially configure the plurality of power circuits to concurrently perform the memory access operations.

6 . The apparatus of claim 5 , wherein the controller comprises a multithread controller.

7 . The apparatus of claim 5 , wherein each memory plane of the plurality of memory planes is divided into blocks of data, and wherein the controller is configured to concurrently perform memory access operations on a different relative block of data of the plurality of memory planes.

8 . The apparatus of claim 5 , further comprising:
a plurality of access line driver circuits, each access line driver circuit of the plurality of access line driver circuits associated with a respective one of the plurality of memory planes and coupled to a respective plurality of global access lines associated with the respective one of the plurality of memory planes.

9 . The apparatus of claim 8 , wherein the power control circuit is further configured to serially configure the plurality of access line drivers to concurrently perform memory access operations.

10 . The apparatus of claim 8 , wherein each power circuit of the plurality of power circuits is associated with the respective one of the plurality of memory planes and coupled to a respective one of the plurality of access line driver circuits,

11 . The apparatus of claim 10 , wherein each power circuit of the plurality of power circuits configured to provide voltages to the respective one of the plurality of access line driver circuits to be provided by the respective one of the plurality of access line driver circuits to a global access line of the respective plurality of global access lines associated with the respective one of the plurality of memory planes.

12 . The apparatus of claim 5 , further comprising a plurality of page buffers, each of the plurality of page buffers coupled to a respective one of the plurality of memory planes and configured to provide data to or receive data from the respective one of the plurality of memory planes.

13 . A method, comprising:
receiving a plurality of memory command and address pairs at a memory, wherein each pair of the plurality of memory command and address pairs is associated with a different memory plane of the memory than another pair of the plurality of memory command and address pairs; responsive to receiving the plurality of memory command and address pairs, configuring, for concurrent memory access operations, power circuits coupled to respective driver circuits of respective memory planes, each memory plane of the respective memory planes associated with a respective pair of the plurality of memory command and address pairs; and retrieving, in parallel, data from each memory plane associated with the respective pair of the plurality of memory command and address pairs during the concurrent memory access operations.

14 . The method of claim 13 , wherein configuring, for the concurrent memory access operations, the power circuits coupled to the respective driver circuits of the respective memory planes comprises configuring the respective driver circuits of the respective memory planes.

15 . The method of claim 14 , wherein configuring the respective driver circuits of respective memory planes comprises configuring, serially, a respective driver circuit of the driver circuits and a respective power circuit of the power circuits based on the respective pair of the plurality of memory command and address pairs.

16 . The method of claim 14 , further comprising providing respective global voltages to each respective driver circuit associated with a corresponding memory plane of the respective memory planes.

17 . The method of claim 13 , further comprising providing respective voltages along respective access lines from each respective driver circuit to the respective memory plane.

18 . The method of claim 13 , wherein retrieving, in parallel, the data from each of the memory planes associated with the respective pair of plurality of memory command and address pairs comprises concurrently charging a respective bitline of each of the memory planes associated with the group of memory command and address pairs.

19 . The method of claim 18 , wherein retrieving, in parallel, data from each of the memory planes associated with the respective pair of the plurality of memory command and address pairs further comprises concurrently sensing the data at each of the memory planes associated with the respective pair of the plurality of memory command and address pairs.

20 . The method of claim 19 , wherein retrieving, in parallel, data from each of the memory planes associated with the group of memory command and address pairs further comprises concurrently latching the data at a respective page buffer coupled to each of the memory planes associated with the respective pair of the plurality of memory command and address pairs.

Assignees

• Micron Technology Inc

Inventors

• Pekny Theodore T
• Park Jae-Kwan
• Moschiano Violante
• Incarnati Michele
• Santis Luca De

Classifications

• G11C2207/2209

  Concurrent read and write · CPC title

• G11C7/22 Primary

  Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management · CPC title

• G11C16/26

  Sensing or reading circuits; Data output circuits · CPC title

• G06F13/1668

  Details of memory controller · CPC title

• G11C16/08

  Address circuits; Decoders; Word-line control circuits · CPC title