Apparatuses and methods for concurrently accessing different memory planes of a memory

Patent metadata

Field	Value
Publication number	US-10083727-B2
Application number	US-201715614072-A
Country	US
Kind code	B2
Filing date	Jun 5, 2017
Priority date	Aug 15, 2014
Publication date	Sep 25, 2018
Grant date	Sep 25, 2018

Abstract

Apparatuses and methods for performing concurrent memory access operations for different memory planes are disclosed herein. An example apparatus may include a memory array having a plurality of memory planes. Each of the plurality of memory planes comprises a plurality of memory cells. The apparatus may further include a controller configured to receive a group of memory command and address pairs. Each memory command and address pair of the group of memory command and address pairs may be associated with a respective memory plane of the plurality of memory planes. The internal controller may be configured to concurrently perform memory access operations associated with each memory command and address pair of the group of memory command and address pairs regardless of page types associated with the pairs of the group (e.g., even if two or more of the memory command and address pairs may be associated with different page types).

First claim

What is claimed is:

1. An apparatus, comprising:
a plurality of memory planes, each memory plane of the plurality of memory planes including a plurality of memory cells;
a plurality of access line driver circuits, wherein an access line driver circuit of the plurality of access line driver circuits is configured to provide voltages to access lines of a respective memory plane of the plurality of memory planes;
a controller coupled to the plurality of access line driver circuits, the controller configured to configure the plurality of access line driver circuits for concurrent memory access operations, the controller further configured to concurrently access the plurality of memory planes after configuring each of the plurality of access line driver circuits during the concurrent memory access operations; and
a plurality of power circuits, each power circuit of the plurality of power circuits associated to a respective one of the plurality of memory planes and coupled to a respective one of the plurality of access line driver circuits, each power circuit of the plurality of power circuits configured to provide voltages to the respective one of the plurality of access line driver circuits.

2. The apparatus of claim 1 wherein the controller is configured to serially configure the plurality of access line driver circuits for concurrent memory access operations.

3. The apparatus of claim 1 wherein the controller is configured to concurrently and independently configure the plurality of access line driver circuits for concurrent memory operation.

4. The apparatus of claim 1 wherein the controller comprises a plurality of control circuits, each control circuit of the plurality associated with a respective one of the plurality of memory planes and configured to concurrently and independently configure the respective one of the plurality of memory planes for concurrent memory access operations responsive to memory command and address pairs directed to the respective one of the plurality of memory planes.

5. The apparatus of claim 1 wherein the controller is configured to control each of the plurality of access line driver circuits to provide voltages to different respective access lines within the respective memory plane of the plurality of memory planes.

6. The apparatus of claim 1 wherein the controller is further configured to configure the plurality of power circuits for to provide the voltages the respective one of the plurality of access line driver circuits to be provided to access lines of the respective memory plane of the plurality of memory planes for the concurrent memory access operations.

7. An apparatus, comprising:
a memory array comprising a plurality of memory planes, wherein each of the plurality of memory planes comprises a plurality of memory cells;
a controller configured to concurrently perform memory access operations on each memory plane of the plurality of memory planes for a corresponding memory command and address pair regardless of page types associated with the pairs of the group;
a plurality of access line driver circuits; and
a plurality of power circuits, each power circuit of the plurality of power circuits associated to a respective one of the plurality of memory planes and coupled to a respective one of the plurality of access line driver circuits, each power circuit of the plurality of power circuits configured to provide voltages to the respective one of the plurality of access line driver circuits to be provided by the respective one of the plurality of access line driver circuits to a global access line of the respective plurality of global access lines associated with a respective one of the plurality of memory planes.

8. The apparatus of claim 7 wherein the controller comprises a multithread controller.

9. The apparatus of claim 7 wherein the each memory plane of the plurality of memory planes is divided into blocks of data, and wherein the controller is configured to concurrently perform memory access operations on a different relative block of data of the plurality of memory planes.

10. The apparatus of claim 7 , wherein each access line driver circuit of the plurality of access line driver circuits associated to the respective one of the plurality of memory planes and coupled to a respective plurality of global access lines associated with the respective one of the plurality of memory planes.

11. The apparatus of claim 10 wherein the controller comprises: an access control circuit configured to serially configure the plurality of access line drivers to concurrently perform memory access operations.

12. The apparatus of claim 7 wherein the controller comprises:
a power control circuit configured to serially configure the plurality of power circuits to concurrently perform memory access operations.

13. The apparatus of claim 7 , further comprising a plurality of page buffers, each of the plurality of page buffers coupled to a respective one of the plurality of memory planes and configured to provide data to or receive data from the respective one of the plurality of memory planes.

14. An apparatus, comprising:
a memory array comprising a plurality of memory planes;
a controller configured to receive a group of memory command and address pairs, wherein each memory command and address pair of the group of memory command and address pairs is associated with a respective memory plane of the plurality of memory planes, the controller configured to concurrently perform memory access operations on each memory plane of the plurality of memory planes for a corresponding memory command and address pair, wherein the controller is a multithread controller including a plurality of control threads, each control thread of the plurality of control threads configured to concurrently configure power circuits of the plurality of power circuits that are coupled to each respective memory plane of the plurality of memory planes to provide respective voltages; and
a plurality of power circuits, wherein a power circuit of the plurality of power circuits is configured to provide two or more voltages to an access line driver circuit of a plurality of access line driver circuits.

15. The apparatus of claim 14 wherein the each memory plane of the plurality of memory planes is divided into blocks of data, and wherein the controller is configured to concurrently perform memory access operations on a different relative block of data of the plurality of memory planes.

16. The apparatus of claim 14 wherein each control thread is further configured to configure the plurality of access line driver circuits that are coupled to each respective memory plane of the plurality of memory planes to provide the voltages to different access lines of the respective memory plane of the plurality of memory planes.

17. The apparatus of claim 14 , further comprising a plurality of page buffers, each page buffer of the plurality coupled to a respective memory plane of the plurality of memory planes, and wherein each control thread of the plurality of control threads is further configured to control and receive data from a respective one of the plurality of page buffers.

18. The apparatus of claim 14 , wherein each control thread of the plurality of control threads may independently and concurrently process a respective memory command and address pair of the group of memory command and address pairs directed to a respective memory plane of the plurality of memory planes.

Assignees

• Micron Technology Inc

Inventors

• Pekny Theodore T
• Park Jae-Kwan
• Moschiano Violante
• Incarnati Michele
• De Santis Luca

Classifications

• G11C2207/2209

  Concurrent read and write · CPC title

• G11C16/10 Primary

  Programming or data input circuits · CPC title

• G11C16/08

  Address circuits; Decoders; Word-line control circuits · CPC title

• G06F13/1668

  Details of memory controller · CPC title

• G11C7/22 Primary

  Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management · CPC title