Semiconductor devices with improved thermal and electrical performance

Patent metadata

Field	Value
Publication number	US-10373897-B2
Application number	US-201615376756-A
Country	US
Kind code	B2
Filing date	Dec 13, 2016
Priority date	Dec 18, 2015
Publication date	Aug 6, 2019
Grant date	Aug 6, 2019

Abstract

A device may include a carrier, a semiconductor chip arranged over a first surface of the carrier, and an encapsulation body comprising six side surfaces and encapsulating the semiconductor chip. A second surface of the carrier opposite to the first surface of the carrier is exposed from the encapsulation body. The device may further include electrical contact elements electrically coupled to the semiconductor chip and protruding out of the encapsulation body exclusively through two opposing side surfaces of the encapsulation body which have the smallest surface areas of all the side surfaces of the encapsulation body, and an electrically insulating layer arranged over the exposed second surface of the carrier.

First claim

What is claimed is:

1. A device, comprising:
a carrier;
a semiconductor chip arranged over a first surface of the carrier;
an encapsulation body comprising six side surfaces and encapsulating the semiconductor chip, wherein a second surface of the carrier opposite to the first surface of the carrier is exposed from the encapsulation body;
electrical contact elements electrically coupled to the semiconductor chip and protruding out of the encapsulation body exclusively through two opposing side surfaces of the encapsulation body which have the smallest surface areas of all the side surfaces of the encapsulation body;
a first material deposited over one or more of the electrical contact elements;
and a second material deposited over the exposed second surface of the carrier;
and wherein the first material is a solder-wettable material, and wherein the second material is a solder non-wettable material.

2. The device of claim 1 ,
wherein the electrically insulating layer comprises at least one of a silicon dioxide, a fluorine-doped silicon dioxide, a carbon-doped silicon dioxide, a polymeric dielectric, a nitride, a metal oxide.

3. The device of claim 1 ,
wherein the electrically insulating layer has a thickness in a range from 50 micrometer to 500 micrometer.

4. The device of claim 1 ,
wherein the carrier comprises a diepad of a leadframe and the electrical contact elements comprise leads of the leadframe.

5. The device of claim 1 ,
wherein the parts of the electrical contact elements protruding out of the encapsulation body are bent in a direction towards a mounting level of the device.

6. The device of claim 1 ,
wherein the device is configured to be mounted on a contact surface using a surface mount technology or a through hole technology.

7. The device of claim 1 , wherein the first material has a melting temperature of less than 260 degrees Celsius.

8. The device of claim 7 , wherein the second material has a melting temperature of at least 260 degrees Celsius.

Assignees

• Infineon Technologies Austria Ag

Inventors

• Otremba Ralf
• Grawert Felix
• Hud Amirul Afiq
• Kirchner Uwe
• Lee Teck Sim
• Lohmann Guenther
• Low Hwee Yin
• Fuergut Edward
• Schmoelzer Bernd
• Schnoy Fabian
• Stueckler Franz

Classifications

• H10W90/766

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W72/07552

  changes in structures or sizes · CPC title

• H10W72/5525

  comprising copper [Cu] · CPC title