3D chip-on-wafer-on-substrate structure with via last process

Patent metadata

Field	Value
Publication number	US-9698081-B2
Application number	US-201615264245-A
Country	US
Kind code	B2
Filing date	Sep 13, 2016
Priority date	May 9, 2014
Publication date	Jul 4, 2017
Grant date	Jul 4, 2017

Abstract

Disclosed herein is a package having a first redistribution layer (RDL) disposed on a first semiconductor substrate and a second RDL disposed on a second semiconductor substrate. The first RDL is bonded to the second RDL. The package further includes an insulating film disposed over the second RDL and around the first RDL and the first semiconductor substrate. A conductive element is disposed in the first RDL. A via extends from a top surface of the insulating film, through the first semiconductor substrate to the conductive element, and a spacer is disposed between the first semiconductor substrate and the via. The spacer extends through the first semiconductor substrate.

First claim

What is claimed is:

1. A package comprising:
a first redistribution layer (RDL) disposed on a first semiconductor substrate;
a second RDL disposed on a second semiconductor substrate, wherein the first RDL is bonded to the second RDL;
an insulating film disposed over the second RDL and around the first RDL and the first semiconductor substrate;
a first conductive element disposed in the first RDL;
a via extending from a top surface of the insulating film, through the first semiconductor substrate to the first conductive element; and
a first spacer disposed between the first semiconductor substrate and the via, wherein the first spacer extends through the first semiconductor substrate.

2. The package of claim 1 , wherein a first sidewall of the first spacer is aligned with a sidewall of the insulating film, and wherein a second sidewall of the first spacer opposite the first sidewall contacts the first semiconductor substrate.

3. The package of claim 1 , wherein top surfaces of the first spacer and the first semiconductor substrate are substantially level, and wherein bottom surfaces of the first spacer and the first semiconductor substrate are substantially level.

4. The package of claim 1 further comprising a second spacer disposed between the via and the first spacer.

5. The package of claim 4 , wherein the second spacer extends from the top surface of the insulating film through the first semiconductor substrate to the first conductive element.

6. The package of claim 4 further comprising a second conductive element disposed in the second RDL, wherein the via extends to the second conductive element.

7. The package of claim 6 further comprising a third spacer extending from the first conductive element to the second conductive element, wherein the third spacer is disposed between the via and the first RDL, and wherein the third spacer is further disposed between the via and the second RDL.

8. The package of claim 7 wherein the third spacer is spaced laterally apart from the second spacer.

9. A package comprising:
a first die comprising:
a first semiconductor substrate;
first redistribution layers (RDLs) comprising a first conductive element;
a conductive via extending through the first semiconductor substrate and the first RDLs; and
a first spacer disposed between a sidewall of the conductive via and a sidewall of the first semiconductor substrate;

a second die bonded to the first die, wherein the second die comprises:
a second semiconductor substrate; and
second RDLs directly bonded to the first RDLs and comprising a second conductive element, wherein the conductive via extends from the first conductive element to the second conductive element; and

an insulating film extending along sidewalls of the first die, wherein the insulating film extends across an interface between the first spacer and the first semiconductor substrate.

10. The package of claim 9 , wherein a line extending along a sidewall of the first spacer opposite the first semiconductor substrate also extends along a sidewall of the insulating film.

11. The package of claim 9 further comprising a second spacer disposed between the sidewall of the conductive via and a sidewall of the first spacer.

12. The package of claim 11 , wherein the conductive via extends through a portion of the insulating film over the first die, and wherein the second spacer is further disposed between the sidewall of the conductive via and a sidewall of the insulating film.

13. The package of claim 11 , wherein the second spacer extends from a surface of the insulating film over the first die to the second conductive element.

14. The package of claim 11 , wherein the insulating film contacts a surface of the second RDLs bonded to the first RDLs.

15. The package of claim 9 , wherein the first spacer contacts the insulating film.

16. A semiconductor package comprising:
a first semiconductor substrate;
first redistribution layers (RDLs) over the first semiconductor substrate, wherein the first RDLs comprise a first conductive line;
second RDLs over and bonded to the first RDLs, wherein the second RDLs comprise a second conductive line;
a second semiconductor substrate over the second RDLs;
an insulation film over and extending along sidewalls of second semiconductor substrate and the second RDLs;
a conductive via extending from a top surface of the insulating film to the first conductive line and the second conductive line;
a first spacer disposed between the conductive via and the second semiconductor substrate; and
a second spacer between the first spacer and the second semiconductor substrate, wherein the second spacer extends through the second semiconductor substrate, and wherein the insulating film is disposed directly over the second spacer.

17. The semiconductor package of claim 16 , wherein a first lateral dimension measured between opposing sidewalls of the first RDLs is greater than a second lateral dimension measured between opposing sidewalls of the second RDLs.

18. The semiconductor package of claim 16 , wherein the second spacer does not extend into the second RDLs.

19. The semiconductor package of claim 16 , wherein the first spacer extends from the top surface of the insulating film to the first conductive line.

20. The semiconductor package of claim 16 , wherein the conductive via contacts the first conductive line and the second conductive line.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Yu Chen-Hua
• Chen Ming-Fa
• Tsai Wen-Ching

Classifications

• H10W99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10W20/0238

  comprising etching via holes through pads or through electrodes · CPC title

• H10W20/0265

  characterised by the sidewall insulation · CPC title

• H10W20/481

  on the rear surfaces of the wafers or substrates · CPC title

• H10W20/2125

  Top-view shapes · CPC title