Method of manufacturing integrated fan-out package

Patent metadata

Field	Value
Publication number	US-10366966-B1
Application number	US-201815981929-A
Country	US
Kind code	B1
Filing date	May 17, 2018
Priority date	May 17, 2018
Publication date	Jul 30, 2019
Grant date	Jul 30, 2019

Abstract

A method of manufacturing an integrated fan-out (InFO) package includes at least the following steps. A package array is formed. A dielectric layer and a core material layer are sequentially formed on a first carrier. A portion of the core material layer is removed to form a core layer having a plurality of cavities. The first carrier, the dielectric layer, and the core layer are attached onto the package array such that the core layer is located between the dielectric layer and the package array. The first carrier is removed from the dielectric layer. A plurality of first conductive patches is formed on the dielectric layer above the cavities.

First claim

What is claimed is:

1. A method of manufacturing an integrated fan-out (InFO) package, comprising:
forming a package array;
sequentially forming a dielectric layer and a core material layer on a first carrier;
removing a portion of the core material layer to form a core layer having a plurality of cavities;
attaching the first carrier, the dielectric layer, and the core layer onto the package array such that the core layer is located between the dielectric layer and the package array;
removing the first carrier from the dielectric layer; and
forming a plurality of first conductive patches on the dielectric layer above the plurality of cavities.

2. The method according to claim 1 , further comprising:
singulating the package array, the dielectric layer, and the core layer.

3. The method according to claim 1 , wherein the portion of the core material layer is removed by a punching process or a photolithography process.

4. The method according to claim 1 , wherein the step of forming the package array comprises:
providing a second carrier;
forming a first redistribution structure over the second carrier;
forming a plurality of through interlayer vias (TIV) and a plurality of dies over the first redistribution structure;
forming an encapsulant encapsulating the plurality of dies and the plurality of TIVs;
forming a second redistribution structure over the plurality of dies, the plurality of TIVs, and the encapsulant;
forming an insulating layer over the first redistribution structure opposite to the plurality of dies.

5. The method according to claim 4 , wherein the step of forming the package array further comprises:
forming a plurality of second conductive patches over the insulating layer, wherein the plurality of second conductive patches are located inside of the plurality of cavities of the core layer.

6. The method according to claim 1 , further comprising:
forming a vent in the core layer.

7. The method according to claim 1 , further comprising:
forming a vent in the dielectric layer.

8. A method of manufacturing an integrated fan-out (InFO) package, comprising:
forming a package array;
placing a plurality of core patterns on the package array, wherein each of the plurality of core patterns comprises a plurality of cavities;
forming a dielectric layer on the plurality of core patterns;
forming a plurality of first conductive patches on the dielectric layer above the plurality of cavities.

9. The method according to claim 8 , further comprising:
singulating the package array.

10. The method according to claim 8 , wherein the plurality of cavities of the plurality of core patterns are formed by a punching process or a photolithography process.

11. The method according to claim 8 , wherein the plurality of core patterns are placed on the package array through a pick-and-place process.

12. The method according to claim 8 , wherein the step of forming the package array comprises:
providing a carrier;
forming a first redistribution structure over the carrier;
forming a plurality of through interlayer vias (TIV) and a plurality of dies over the first redistribution structure;
forming an encapsulant encapsulating the plurality of dies and the plurality of TIVs;
forming a second redistribution structure over the plurality of dies, the plurality of TIVs, and the encapsulant;
forming an insulating layer over the first redistribution structure opposite to the plurality of dies.

13. The method according to claim 12 , wherein the step of forming the package array further comprises:
forming a plurality of second conductive patches over the insulating layer, wherein the plurality of second conductive patches are located inside of the plurality of cavities of the plurality of core patterns.

14. The method according to claim 8 , further comprising:
forming a vent in each of the plurality of core patterns.

15. The method according to claim 8 , further comprising:
forming a vent in the dielectric layer.

16. A method of manufacturing an integrated fan-out (InFO) package, comprising:
forming a package array;
forming a core layer having a plurality of cavities over the package array;
forming a dielectric layer on the core layer;
providing a conductive foil;
punching the conductive foil to form a plurality of first conductive patches;
attaching the plurality of first conductive patches on the dielectric layer above the plurality of cavities.

17. The method according to claim 16 , wherein the plurality of first conductive patches are attached to the dielectric layer through an adhesive layer.

18. The method according to claim 16 , wherein the step of attaching the plurality of first conductive patches on the dielectric layer comprises:
placing the plurality of first conductive patches on the dielectric layer through a pick-and-place process.

19. The method according to claim 16 , wherein the step of punching the conductive foil and the step of attaching the plurality of first conductive patches on the dielectric layer comprises:
placing the conductive foil on a carrier film;
punching the conductive foil to remove a portion of the conductive foil and to form the plurality of first conductive patches;
attaching the carrier film and the plurality of first conductive patches onto the dielectric layer such that the plurality of first conductive patches are located between the carrier film and the dielectric layer; and
removing the carrier film from the plurality of first conductive patches.

20. The method according to claim 16 , wherein the step of attaching the plurality of first conductive patches on the dielectric layer comprises:
providing a stencil over the dielectric layer, wherein the stencil comprises a plurality of apertures exposing the dielectric layer;
distributing the plurality of first conductive patches over the stencil; and
vibrating the plurality of first conductive patches such that the plurality of first conductive patches are driven into the plurality of apertures of the stencil.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Wan Albert
• Hsieh Ching-Hua
• Tsai Chung-Hao
• Wang Chuei-Tang
• Shih Chao-Wen
• Pu Han-Ping
• Hwang Chien-Ling
• Lee Pei-Hsuan
• Tang Tzu-Chun
• Chiu Yu-Ting
• Kuo Jui-Chang

Classifications

• H10W72/0198

  batch processes · CPC title

• H10W70/099

  Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers · CPC title

• H10W72/874

  On different surfaces · CPC title

• H10W72/9413

  on encapsulations · CPC title

• H10W44/248

  for antennas · CPC title