Integrated circuit protection during high-current ESD testing

Patent metadata

Field	Value
Publication number	US-10359461-B2
Application number	US-201715834184-A
Country	US
Kind code	B2
Filing date	Dec 7, 2017
Priority date	Apr 13, 2012
Publication date	Jul 23, 2019
Grant date	Jul 23, 2019

Abstract

A method of protecting devices within an integrated circuit during electro-static discharge (ESD) testing using an ESD test system is provided. The method includes applying a direct current (DC) bias voltage to an input of at least one device of the integrated circuit and applying an ESD simulated signal to at least one other input of the integrated circuit. The applied ESD simulated signal is conducted along a first current path to a first ground, while a low-current signal associated with the at least one device is conducted along a second current path to the second ground. The DC bias voltage is maintained between the input of the at least one device and the second ground at a substantially constant value in response to a signal variation on the second ground that results from the applied ESD simulated signal.

First claim

What is claimed is:

1. A method of protecting devices within an integrated circuit during electro-static discharge (ESD) testing using an ESD test system, the method comprising:
connecting to an input of the at least one device of the integrated circuit a first connection having a center conductor and an outer conductor, the center conductor of the first connection delivering a direct current (DC) bias voltage to the input of the at least one device;
applying an ESD simulated signal to one other input of the integrated circuit;
conducting the applied ESD simulated signal along a first current path to a first ground;
conducting a low-current signal associated with the at least one device along a second current path to a second ground; and
connecting to the second ground a second connection having a center conductor and an outer conductor, the center conductor of the second connection electrically coupling the outer conductor of the first connection to the second ground, and the outer conductor of the second connection connected to the first ground; and
maintaining the DC bias voltage between the input of the at least one device and the second ground at a substantially constant value in response to a signal variation on the second ground that results from the applied ESD simulated signal.

2. The method of claim 1 , wherein the maintaining of the DC bias voltage comprises capacitively coupling the DC bias voltage on the input of the at least one device to the second ground using a charge storage device.

3. The method of claim 2 , wherein the charge storage device comprises a capacitor having a capacitance in the range of about 1-100 Nanofarads (nF).

4. The method of claim 1 , wherein the first current path associated with the ESD simulated signal conducted to the first ground is separated from the second current path associated with the low-current signal conducted to the second ground.

5. The method of claim 1 , wherein the first connection comprises a first coaxial cable, and wherein the second connection comprises a second coaxial cable.

6. The method of claim 1 , wherein the ESD simulated signal comprises a transmission line pulse (TLP) signal that simulates a human body model (HBM) electro-static discharge (ESD) discharge signal.

7. The method of claim 1 , wherein the first ground comprises a system ground associated with the ESD test system generating the ESD simulated signal.

8. The method of claim 1 , wherein the second ground comprises a silicon ground associated with the integrated circuit.

9. The method of claim 1 , wherein the ESD simulated signal is applied to a test input on the integrated circuit.

10. The method of claim 9 , wherein the test input comprises an input associated with an electro-static discharge (ESD) protection device.

11. The method of claim 10 , wherein the electro-static discharge (ESD) protection device comprises:
a diode network having a first diode and a second diode; and
a power clamp circuit,
wherein, the first diode for conducting a positive ESD pulse to the power clamp circuit, wherein upon the power clamp circuit receiving the positive ESD pulse, the power clamp circuit providing a conductive path to the first ground for the positive ESD pulse; and
wherein the second diode for conducting a negative ESD pulse to the power clamp circuit, wherein upon the power clamp circuit receiving the negative ESD pulse, the power clamp circuit providing a conductive path to the first ground for the negative ESD pulse.

12. The method of claim 1 , wherein the signal variation on the second ground is generated by a wiring resistance associated with an electrical connection between the first ground and the second ground.

Assignees

• IBM

Inventors

• Chang Shunhua
• Di Sarro James Paul
• Gauthier Jr Robert J
• Jack Nathan
• Mitra Souvick

Classifications

• G01R31/002 Primary

  where the device under test is an electronic circuit · CPC title

• H02H9/046 Primary

  responsive to excess voltage appearing at terminals of integrated circuits · CPC title

• H01L27/0248

  Electricity · mapped topic

• G01R31/2851

  Testing of integrated circuits [IC] (G01R31/317 takes precedence; testing individual devices G01R31/26; testing printed circuits G01R31/2801) · CPC title

• H05K9/0067

  Devices for protecting against damage from electrostatic discharge · CPC title