Methods and apparatus for MOS capacitors in replacement gate process

Patent metadata

Field	Value
Publication number	US-10354920-B2
Application number	US-201615231215-A
Country	US
Kind code	B2
Filing date	Aug 8, 2016
Priority date	Nov 22, 2011
Publication date	Jul 16, 2019
Grant date	Jul 16, 2019

Abstract

Methods and apparatus for polysilicon MOS capacitors in a replacement gate process. A method includes disposing a gate dielectric layer over a semiconductor substrate; disposing a polysilicon gate layer over the dielectric layer; patterning the gate dielectric layer and the polysilicon gate layer to form a plurality of polysilicon gates spaced by at least a minimum polysilicon to polysilicon pitch; defining a polysilicon resistor region containing at least one of the polysilicon gates and not containing at least one other of the polysilicon gates, which form dummy gates; depositing a mask layer over an inter-level dielectric layer; patterning the mask layer to expose the dummy gates; removing the dummy gates and the gate dielectric layer underneath the dummy gates to leave trenches in the inter-level dielectric layer; and forming high-k metal gate devices in the trenches in the inter-level dielectric layer. An apparatus produced by the method is disclosed.

First claim

What is claimed is:

1. A method, comprising:
disposing a gate dielectric layer over a semiconductor substrate;
disposing a polysilicon gate layer over the gate dielectric layer;
patterning the gate dielectric layer and the polysilicon gate layer to form a plurality of polysilicon gates spaced by at least a minimum polysilicon-to-polysilicon pitch;
forming an inter-level dielectric layer over the semiconductor substrate and filling the spaces between the plurality of polysilicon gates and surrounding the plurality of polysilicon gates such that a top surface of the inter-level dielectric layer is level with top surfaces of polysilicon material of the plurality of polysilicon gates;
defining a polysilicon resistor region containing a first set of polysilicon gates, the first set of polysilicon gates comprising at least one of the plurality of polysilicon gates and not containing at least one other of the plurality of polysilicon gates, which form dummy gates;
depositing a mask layer over the inter-level dielectric layer;
patterning the mask layer to expose the dummy gates;
removing the dummy gates and the gate dielectric layer underneath the dummy gates to leave trenches in the inter-level dielectric layer; and
forming metal gate devices in the trenches in the inter-level dielectric layer.

2. The method of claim 1 , further comprising:
forming a connector electrically coupling the first set of polysilicon gates in the polysilicon resistor region together, each of the polysilicon gates of the first set of polysilicon gates forming a top plate of a polysilicon MOS capacitor, the gate dielectric of each of the polysilicon gates of the first set of polysilicon gates forming a capacitor dielectric.

3. The method of claim 2 , further comprising forming a conductive region in the semiconductor substrate underlying the first set of polysilicon gates in the polysilicon resistor region, the conductive region forming a bottom plate of the MOS capacitors.

4. The method of claim 3 , wherein a total capacitance obtained is the sum of the capacitance provided by each of the polysilicon MOS capacitors.

5. The method of claim 1 , wherein forming the metal gate device further comprises forming a high-k dielectric comprising hafnium.

6. The method of claim 1 , wherein forming the metal gate device further comprises forming a metal gate comprising titanium or aluminum.

7. The method of claim 1 further comprising:
implanting the first set of polysilicon gates in the polysilicon resistor region with dopants to form polysilicon resistor material.

8. The method of claim 1 , wherein forming the metal gate device further comprises forming a high-k dielectric comprising a material selected from the group consisting essentially of hafnium silicate, zirconium silicate, hafnium dioxide, and zirconium dioxide.

9. A method comprising:
forming a first gate stack in a first region of a substrate and a second gate stack in a second region of the substrate, the first gate stack comprising a first gate dielectric in contact with a first polysilicon gate, the second gate stack comprising a second gate dielectric in contact with a second polysilicon gate;
performing a polysilicon resistor implant process on the second polysilicon gate;
forming a dielectric layer over the substrate and between the first gate stack and the second gate stack, the dielectric layer contacting at least one sidewall of each of the first gate stack and the second gate stack;
planarizing the dielectric layer such that a top surface of the dielectric layer is level with a top surface of the first polysilicon gate of the first gate stack and a top surface of the second polysilicon gate of the second gate stack; and
replacing the first gate stack with a third gate stack, the third gate stack comprising a high-k gate dielectric and a metal gate.

10. The method of claim 9 , wherein replacing the first gate stack with the third gate stack comprises;
forming a mask over the second gate stack;
removing the first polysilicon gate and the first gate dielectric to form a first trench in the dielectric layer;
forming the high-k gate dielectric in the first trench; and
forming the metal gate on the high-k gate dielectric.

11. The method of claim 9 further comprising a plurality of gate stacks in the second region, each of the gate stacks of the plurality of gate stacks comprising a gate dielectric layer and a polysilicon gate.

12. The method of claim 11 further comprising:
forming a connector electrically coupling the polysilicon gates of the second gate stack and the plurality of gate stacks together, each of the polysilicon gates forming a top plate of a polysilicon MOS capacitor, the gate dielectric of each of the polysilicon gates forming a capacitor dielectric.

13. The method of claim 12 further comprising:
doping the substrate underlying the polysilicon gates in the second region to form a doped region, the doped region forming a bottom plate of the polysilicon MOS capacitor.

14. The method of claim 11 , wherein a first edge of one of the polysilicon gates in the second region is spaced apart from a corresponding second edge of another polysilicon gate by a minimum pitch, and wherein the minimum pitch is determined by processing limitations for forming metal gates.

15. The method of claim 9 , wherein the second gate dielectric comprises silicon oxynitride.

16. The method of claim 9 , wherein the metal gate comprises titanium or aluminum.

17. A method comprising:
forming a polysilicon layer over a gate dielectric layer over a substrate;
patterning the polysilicon layer and the gate dielectric layer to form a dummy gate and a dummy gate dielectric in a first region and a plurality of polysilicon gates and a plurality of gate dielectrics in a second region;
removing the dummy gate and the dummy gate dielectric;
forming a high-k gate dielectric where the dummy gate and the dummy gate dielectric were removed; and
forming a metal gate on the high-k gate dielectric;
planarizing the metal gate and the polysilicon layer of the plurality of polysilicon gates such that a top surface of the metal gate is coplanar with top surfaces of the polysilicon layer of the plurality of polysilicon gates; and
doping the substrate in the second region to form a doped region, the doped region being a bottom plate for MOS capacitors, a top surface of the doped region being planar, and the top surface of the doped region extending between adjacent gate dielectrics of the plurality of gate dielectrics.

18. The method of claim 17 further comprising:
forming a conductive connector over and electrically coupled to the polysilicon gates of the plurality of polysilicon gates in the second region of the substrate, the electrically coupled plurality of polysilicon gates forming top plates of MOS capacitors.

19. The method of claim 18 , wherein the conductive connector comprises vias contacting the plurality of polysilicon gates and an overlying common conductive connector contacting the vias.

20. The method of claim 17 , wherein the gate dielectrics have a different material composition than the high-k gate dielectric.

Assignees

• Taiwan Semiconductor Mfg Co Ltd
• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Wang Pai-Chieh
• Hsieh Tung-Heng
• Huang Yimin
• Chen Chung-Hui

Classifications

• H10D84/813

  Combinations of field-effect devices and capacitor only · CPC title

• H10D84/817

  Combinations of field-effect devices and resistors only · CPC title

• H01L27/0629

  Electricity · mapped topic

• H01L29/401

  Electricity · mapped topic

• H01L27/0727

  Electricity · mapped topic