Diode string implementation for electrostatic discharge protection

Patent metadata

Field	Value
Publication number	US-9484338-B2
Application number	US-201314049239-A
Country	US
Kind code	B2
Filing date	Oct 9, 2013
Priority date	Oct 9, 2013
Publication date	Nov 1, 2016
Grant date	Nov 1, 2016

Abstract

A diode string having a plurality of diodes for ESD protection of a CMOS IC device comprises a first diode and a last diode in the diode string, wherein the first diode and the last diode are both formed on a bottom layer in a silicon substrate, and remaining diodes in the diode string. The remaining diodes are formed on a top layer placed on top of the bottom layer. The diode string further comprises a plurality of conductive lines that connect the first diode and the last diode on the bottom layer sequentially with the remaining diodes on the top layer to form a three dimensional (3D) structure of the diode string.

First claim

What is claimed is:

1. A diode string having a plurality of diodes for ElectroStatic Discharge (ESD) protection of a CMOS IC device, comprising:
a first diode and a last diode in the diode string, wherein the first diode and the last diode are both formed on a bottom layer in a silicon substrate, and wherein the first diode and the last diode are separated with a first shallow trench isolation (STI) region in the bottom layer;
a plurality of remaining diodes in the diode string, wherein the remaining diodes are all formed on at least one upper layer above the bottom layer, wherein the plurality of the remaining diodes on the upper layer are structurally isolated from the first diode and the last diode on the bottom layer, and wherein any two adjacent diodes of the remaining diodes in the at least one upper layer are separated from each other with at least a second STI region in the upper layer; and
a plurality of conductive lines that connect the first diode and the last diode on the bottom layer sequentially with the remaining diodes on the at least one upper layer to form a three dimensional (3D) structure of the diode string.

2. The diode string of claim 1 , wherein:
the upper layer is separated from the bottom layer.

3. The diode string of claim 1 , wherein:
the upper layer is a thin semiconductor substrate layer.

4. The diode string of claim 1 , wherein:
each diode in the diode string is formed in a N-well with a P+ node and a N+ node separated by a shallow trench isolation (STI) region.

5. The diode string of claim 4 , wherein:
the P+ node of the first diode connects to power rail V DD to serve as an anode for the diode string and the N+ node of the last diode connects to ground rail V SS to serve as a cathode for the diode string.

6. A diode string having a plurality of diodes for ElectroStatic Discharge (ESD) protection of a CMOS IC device, comprising:
a first diode and a last diode in the diode string, wherein the first diode and the last diode are both formed on a bottom layer in a silicon substrate, and wherein the first diode and the last diode are separated with a first shallow trench isolation (STI) region in the bottom layer;
a plurality of remaining diodes in the diode string, wherein the remaining diodes are formed on a plurality of device layers stacked above the bottom layer, and wherein any two adjacent diodes of the remaining diodes formed in one of the device layers are separated from each other with at least a second STI region in the one of the device layers; and
a plurality of conductive lines that connect the first diode and the last diode on the bottom layer sequentially with the remaining diodes on the device layers to form a three dimensional (3D) structure of the diode string;
wherein a P+ node of the first diode and an N+ node of the last diode are located adjacent to each other but separated with the first STI region so as to form a parasitic path between the first diode and the last diode.

7. The diode string of claim 6 , wherein:
the bottom layer and the device layers are separated from each other by an interconnect structure comprising at least one conductive line layer or via layer.

8. The diode string of claim 6 , wherein:
the plurality of remaining diodes are connected to each other via intra layer metal connections over the device layers and to diodes on other layers via the conductive lines between the layers.

9. A method for forming a diode string for ElectroStatic Discharge (ESD) protection of a CMOS IC device, comprising:
forming a first diode and a last diode in the diode string comprising a plurality of diodes on a bottom layer on a silicon substrate, wherein the first diode and the last diode are separated with a first shallow trench isolation (STI) region in the bottom layer;
forming all of a plurality of remaining diodes in the diode string on one or more device layers stacked above the bottom layer, wherein the plurality of the remaining diodes on the one or more device layers are structurally isolated from the first diode and the last diode on the bottom layer, and wherein any two adjacent diodes of the remaining diodes formed in one of the device layers are separated from each other with at least a second STI region in the one of the device layers;
connecting the remaining diodes formed on each of the device layers to each of the remaining diodes in the diode string on the same layer sequentially using intra layer metal connections;
connecting the remaining diodes formed on the one or more device layers to the first and the last diodes on the bottom layer as well as to remaining diodes on other device layers using a plurality of conductive lines so that the first diode, the last diode and the remaining diodes are connected sequentially to form a three dimensional (3D) structure of the diode string.

10. The method of claim 9 , wherein:
separating the bottom layer and the device layers are separated from each other by an interconnect structure comprising at least one conductive line layer or via layer.

11. The method of claim 9 , further comprising:
forming each diode in the diode string in an N-well with a P+ node and an N+ node separated by a shallow trench isolation (STI) region.

12. The method of claim 11 , further comprising:
connecting the P+ node of the first diode to power rail V DD to serve as an anode for the diode string and connecting the N+ node of the last diode to ground rail V SS to serve as a cathode for the diode string.

13. The method of claim 9 , further comprising:
connecting the plurality of diodes to each other via intra layer metal connections on the layer.

14. The method of claim 9 , further comprising:
connecting ones of the plurality of diodes to others of the plurality of diodes on different ones of the bottom layer or device layers via the conductive lines.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Tsai Tsung-Che
• Lee Jam-Wem

Classifications

• H02H9/046

  responsive to excess voltage appearing at terminals of integrated circuits · CPC title

• H10D8/80

  PNPN diodes, e.g. Shockley diodes or break-over diodes · CPC title

• H10D89/611 Primary

  using diodes as protective elements · CPC title

• H10D88/00

  Three-dimensional [3D] integrated devices · CPC title

• H10D84/221

  of only diodes · CPC title