Suspending translation look-aside buffer purge execution in a multi-processor environment

Patent metadata

Field	Value
Publication number	US-10353825-B2
Application number	US-201715625444-A
Country	US
Kind code	B2
Filing date	Jun 16, 2017
Priority date	Jun 16, 2017
Publication date	Jul 16, 2019
Grant date	Jul 16, 2019

Abstract

A method for operating translation look-aside buffers, TLBs, in a multiprocessor system. A purge request is received for purging one or more entries in the TLB. When the thread doesn't require access to the entries to be purged the execution of the purge request at the TLB may start. When an address translation request is rejected due to the TLB purge, a suspension time window may be set. During the suspension time window, the execution of the purge is suspended and address translation requests of the thread are executed. After the suspension window is ended the purge execution may be resumed. When the thread requires access to the entries to be purged, it may be blocked for preventing the thread sending address translation requests to the TLB and upon ending the purge request execution, the thread may be unblocked and the address translation requests may be executed.

First claim

What is claimed is:

1. A system for operating translation look-aside buffers, TLBs, comprising at least one core each having at least one thread, the system being configured for:
receiving a purge request for purging one or more entries in the TLB;
determining if a thread requires access to an entry of the entries to be purged;
when the thread does not require access to the entries to be purged:
starting execution of the purge request in the TLB;
setting a suspension time window;
suspending the execution of the purge during the suspension time window;
executing address translation requests of the thread during the suspension time window;
resuming the purge execution after the suspension window is ended;

when the thread requires access to the entries to be purged:
blocking the thread for preventing the thread sending address translation requests to the TLB;
upon ending the purge request execution, unblocking the thread and executing the address translation requests of the thread.

2. The system of claim 1 , the at least one core supporting a second thread, in case a first thread does not require access to the TLB entries to be purged and the second thread requires access to an entry to be purged, the system being further configured for before starting the execution of the purge request at the TLB:
blocking both the first and second threads for preventing them sending requests to the TLB;
when the purge request has started at both the first and second threads, unblocking the first thread.

3. The system of claim 1 , the at least one core supporting a second thread, when a first thread requires access to at least an entry of the entries to be purged and the second thread does not require access to the entries to be purged, the system being further configured for:
upon the blocking of the first thread starting execution of the purge request at the TLB; setting a suspension time window if an address translation request by the second thread is rejected due to the TLB purge; suspending the execution of the purge during the suspension time window;
executing address translation requests of the second thread during the suspension time window;
resuming the purge execution after the suspension window is ended.

4. The system of claim 1 , the determining if the thread requires access to an entry of the entries to be purged is performed based on a current state of the thread, the system being further configured for before the purge request ends, maintaining the state of the thread un-changed.

5. The system of claim 4 , being further configured for in response to receiving an assignment request for assigning the thread to a process requiring access entries to be purged, blocking the assignment request.

6. A computer program product comprising a computer-readable storage medium having computer-readable program code embodied therewith, the computer-readable program code configured to implement the steps of:
receiving a purge request for purging one or more entries in the TLB;
determining if a thread requires access to an entry of the entries to be purged;
when the thread does not require access to the entries to be purged:
starting execution of the purge request in the TLB;
setting a suspension time window;
suspending the execution of the purge during the suspension time window;
executing address translation requests of the thread during the suspension time window;
resuming the purge execution after the suspension window is ended;

when the thread requires access to the entries to be purged:
blocking the thread for preventing the thread sending address translation requests to the TLB;
upon ending the purge request execution, unblocking the thread and executing the address translation requests of the thread.

7. The computer program product of claim 6 wherein the at least one core supporting a second thread, when a first thread does not require access to the TLB entries to be purged and the second thread requires access to an entry to be purged, the steps further comprises, before starting the execution of the purge request at the TLB:
blocking both the first and second threads for preventing them sending requests to the TLB;
when the purge request has started at both the first and second threads, unblocking the first thread.

8. The computer program product of claim 6 wherein the setting of the suspension time window is performed in response to an address translation request of the thread being rejected due to the TLB purge.

Assignees

• IBM

Inventors

• Brandt Uwe
• Gaertner Ute
• Heller Lisa C
• Helms Markus
• Köhler Thomas
• Lehnert Frank
• Navarro Jennifer A
• Wisniewski Rebecca S

Classifications

• G06F12/1009

  using page tables, e.g. page table structures · CPC title

• G06F2212/30

  Providing cache or TLB in specific location of a processing system · CPC title

• G06F2212/68

  Details of translation look-aside buffer [TLB] · CPC title

• G06F2212/50

  Control mechanisms for virtual memory, cache or TLB · CPC title

• G06F2212/682

  Multiprocessor TLB consistency · CPC title