Operating on translation look-aside buffers in a multiprocessor environment

Patent metadata

Field	Value
Publication number	US-9372805-B2
Application number	US-201314034848-A
Country	US
Kind code	B2
Filing date	Sep 24, 2013
Priority date	Feb 26, 2008
Publication date	Jun 21, 2016
Grant date	Jun 21, 2016

Abstract

An aspect includes a method for operating on translation look-aside buffers (TLBs) in a multiprocessor environment including a plurality of logical partitions as zones. The method includes concurrently receiving a first quiesce request from a first processor of a first zone to quiesce processors of a first set of zones including the first zone and receiving a second quiesce request from a second processor of a second zone to quiesce processors of a second set of zones including the second zone. The second set of zones consists of separate zones from the first set of zones. Based on receiving the first quiesce request, only processors of the first set of zones are quiesced. Based on the processors of the first set of zones being quiesced, a first operation is performed on the TLBs. Based on the first operation being performed, the processors of the first set of zones are un-quiesced.

First claim

What is claimed is:

1. A method for operating on translation look-aside buffers (TLBs) in a multiprocessor environment, the multi-processor environment comprising a plurality of logical partitions as zones, each zone comprising one or more logical processors assigned to physical processors each having at least one of the TLBs, the method comprising:
concurrently receiving a first quiesce request from a first processor of a first zone to quiesce processors of a first set of zones comprising the first zone and receiving a second quiesce request from a second processor of a second zone to quiesce processors of a second set of zones comprising the second zone, the second set of zones consisting of separate and distinct zones from the first set of zones;
based on receiving the first quiesce request, quiescing only processors of the first set of zones;
processing the first quiesce request by a first controller, sending a purge request to a processor, the purge request including a tag identifying the first controller to the processor as the source of the purge request;
based on the processors of the first set of zones being quiesced, performing a first operation on the TLBs;
based on the first operation being performed, un-quiescing the processors of the first set of zones;
based on concurrently receiving the second quiesce request, quiescing only the processors of the second set of zones;
based on the processors of the second set of zones being quiesced, performing a second operation on the TLBs; and
based on the second operation being performed, un-quiescing the processors of the second set of zones.

2. The method of claim 1 wherein a first controller processes the quiesce requests from the processors in the first set of zones in a serial manner and a second controller processes the quiesce requests from the processors in the second set of zones in a serial manner.

3. The method of claim 2 wherein additional quiesce requests are processed by one or more additional controllers in the system, each additional controller configured to process an additional quiesce request overlapping in time with the first quiesce request.

4. The method of claim 1 further comprising:
receiving the first and second quiesce requests at the first processor and the second processor;
responding to the first and second quiesce requests at the first processor; and
responding to the first and second quiesce requests at the second processor.

5. The method of claim 1 further comprising receiving a started indication from the processor in response to the processor acting on the purge request.

6. The method of claim 1 wherein the tag is utilized by the processor to differentiate between the first and second quiesce requests and to coordinate responding to the first quiesce request separately from the second quiesce request.

7. A system for operating on translation look-aside buffers (TLBs) in a multi-processor environment, the system comprising:
a plurality of logical partitions as zones, each zone comprising one or more logical processors assigned to physical processors each having at least one of the TLBs; and
at least two controllers configured to perform a method comprising:
concurrently receiving a first quiesce request from a first processor of a first zone to quiesce processors of a first set of zones comprising the first zone and receiving a second quiesce request from a second processor of a second zone to quiesce processors of a second set of zones comprising the second zone, the second set of zones consisting of separate and distinct zones from the first set of zones;
based on receiving the first quiesce request, quiescing only processors of the first set of zones;
processing the first quiesce request by a first controller, sending a purge request to a processor, the purge request including a tag identifying the first controller to the processor as the source of the purge request;
based on the processors of the first set of zones being quiesced, performing a first operation on the TLBs;
based on the first operation being performed, un-quiescing the processors of the first set of zones;
based on concurrently receiving the second quiesce request, quiescing only the processors of the second set of zones;
based on the processors of the second set of zones being quiesced, performing a second operation on the TLBs; and
based on the second operation being performed, un-quiescing the processors of the second set of zones.

8. The system of claim 7 wherein a first controller processes the quiesce requests from the processors in the first set of zones in a serial manner and a second controller processes the quiesce requests from the processors in the second set of zones in a serial manner.

9. The system of claim 8 wherein additional quiesce requests are processed by one or more additional controllers in the system, each additional controller configured to process an additional quiesce request overlapping in time with the first quiesce request.

10. The system of claim 7 wherein the system is further configured to perform:
receiving the first and second quiesce requests at the first processor and the second processor;
responding to the first and second quiesce requests at the first processor; and
responding to the first and second quiesce requests at the second processor.

11. The system of claim 7 wherein the system is further configured to perform receiving a started indication from the processor in response to the processor acting on the purge request.

12. The system of claim 7 wherein the tag is utilized by the processor to differentiate between the first and second quiesce requests and to coordinate responding to the first quiesce request separately from the second quiesce request.

13. A computer program product for operating on translation look-aside buffers (TLBs) in a multiprocessor environment, the multi-processor environment comprising a plurality of logical partitions as zones, each zone comprising one or more logical processors assigned to physical processors each having at least one of the TLBs, the computer program product comprising:
a tangible storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method comprising:
concurrently receiving a first quiesce request from a first processor of a first zone to quiesce processors of a first set of zones comprising the first zone and receiving a second quiesce request from a second processor of a second zone to quiesce processors of a second set of zones comprising the second zone, the second set of zones consisting of separate and distinct zones from the first set of zones;
based on receiving the first quiesce request, quiescing only processors of the first set of zones;
processing the first quiesce request by a first controller, sending a purge request to a processor, the purge request including a tag identifying the first controller to the processor as the source of the purge request;
based on the processors of the first set of zones being quiesced, performing a first operation on the TLBs;
based on the first operation being performed, un-quiescing the processors of the first set of zones;
based on concurrently receiving the second quiesce request, quiescing only the processors of the second set of zones;
based on the processors of the second set of zones being quiesced, performing a second operation on the TLBs; and
based on the second operation being performed, un-quiescing the processors of the second set of zones.

14. The computer program product of claim 13 wherein a first controller proc

Assignees

• IBM

Inventors

• Heller Lisa C
• Hagspiel Norbert
• Gaertner Ute
• Ulrich Hanno
• Wisniewski Rebecca S

Classifications

• G06F2212/683

  Invalidation · CPC title

• G06F2212/682

  Multiprocessor TLB consistency · CPC title

• G06F12/10

  Address translation · CPC title

• G06F12/1027 Primary

  using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] · CPC title

• G06F9/52

  Program synchronisation; Mutual exclusion, e.g. by means of semaphores · CPC title