Array substrate, manufacturing method thereof, and display panel

Patent metadata

Field	Value
Publication number	US-10347662-B2
Application number	US-201715558688-A
Country	US
Kind code	B2
Filing date	Jun 22, 2017
Priority date	May 19, 2017
Publication date	Jul 9, 2019
Grant date	Jul 9, 2019

Abstract

The present disclosure discloses an array substrate comprising: a substrate; a gate electrode; a gate insulating layer formed on one side of the substrate facing the gate electrode, the gate insulating layer covering the gate electrode; an active layer formed on one side of the gate insulating layer away from the gate electrode and made of an indium gallium zinc tin oxide material; an ohmic contact layer formed on one side of the active layer away from the gate insulating layer and made of a conductive indium gallium zinc oxide material, the ohmic contact layer covering both ends of the active layer; and a source electrode and a drain electrode formed on one side of the ohmic contact layer away from the active layer, the source electrode and the drain electrode being electrically connected to both ends of the active layer by the ohmic contact layer, respectively.

First claim

What is claimed is:

1. An array substrate comprising:
a substrate;
a gate electrode formed on the substrate;
a gate insulating layer formed on one side of the substrate facing the gate electrode, the gate insulating layer covering the gate electrode;
an active layer formed on one side of the gate insulating layer away from the gate electrode and made of an indium gallium zinc tin oxide material;
an ohmic contact layer formed on one side of the active layer away from the gate insulating layer and made of a conductive indium gallium zinc oxide material, the ohmic contact layer covering two opposite end portions of the active layer; and
a source electrode and a drain electrode which are separate from each other formed on one side of the ohmic contact layer away from the active layer, the source electrode and the drain electrode being electrically connected to both ends of the active layer by the ohmic contact layer, respectively,
wherein the active layer is arranged on the gate insulating layer and the ohmic contact layer is arranged on the end portions of the active layer, such that the end portions of the active layer are sandwiched between the ohmic contact layer and the gate insulating layer.

2. The array substrate according to claim 1 , wherein the ohmic contact layer comprises a first ohmic contact block and a second ohmic contact block which are arranged at intervals, the first ohmic contact block covering a first one of the end portions of the active layer and being connected to the source electrode, the second ohmic contact block covering a second one of the end portions of the active layer and being connected to the drain electrode.

3. The array substrate according to claim 2 , wherein the thickness of the active layer is greater than or equal to 400 Å and is less than or equal to 1000 Å, and the thickness of the ohmic contact layer is less than or equal to 500 Å.

4. The array substrate according to claim 1 , wherein the array substrate further comprises:
a passivation layer covering the source electrode, the drain electrode and the active layer, the passivation layer being provided with a via hole for exposing a portion of the drain electrode; and
a pixel electrode formed on one side of the passivation layer away from the source electrode, the pixel electrode being connected to the drain electrode through the via hole.

5. The array substrate according to claim 2 , wherein the array substrate further comprises:
a passivation layer covering the source electrode, the drain electrode and the active layer, the passivation layer being provided with a via hole for exposing a portion of the drain electrode; and
a pixel electrode formed on one side of the passivation layer away from the source electrode, the pixel electrode being connected to the drain electrode through the via hole.

6. The array substrate according to claim 3 , wherein the array substrate further comprises:
a passivation layer covering the source electrode, the drain electrode and the active layer, the passivation layer being provided with a via hole for exposing a portion of the drain electrode; and
a pixel electrode formed on one side of the passivation layer away from the source electrode, the pixel electrode being connected to the drain electrode through the via hole.

7. A display panel comprising an array substrate, the array substrate comprising:
a substrate;
a gate electrode formed on the substrate;
a gate insulating layer formed on one side of the substrate facing the gate electrode, the gate insulating layer covering the gate electrode;
an active layer formed on one side of the gate insulating layer away from the gate electrode and made of an indium gallium zinc tin oxide material;
an ohmic contact layer formed on one side of the active layer away from the gate insulating layer and made of a conductive indium gallium zinc oxide material, the ohmic contact layer covering two opposite end portions of the active layer; and
a source electrode and a drain electrode which are separate from each other formed on one side of the ohmic contact layer away from the active layer, the source electrode and the drain electrode being electrically connected to both ends of the active layer by the ohmic contact layer, respectively,
wherein the active layer is arranged on the gate insulating layer and the ohmic contact layer is arranged on the end portions of the active layer, such that the end portions of the active layer are sandwiched between the ohmic contact layer and the gate insulating layer.

8. The display panel according to claim 7 , wherein the ohmic contact layer comprises a first ohmic contact block and a second ohmic contact block which are arranged at intervals, the first ohmic contact block covering a first one of the end portions of the active layer and being connected to the source electrode, the second ohmic contact block covering a second one of the end portions of the active layer and being connected to the drain electrode.

9. The display panel according to claim 8 , wherein the thickness of the active layer is greater than or equal to 400 Å and is less than or equal to 1000 Å, and the thickness of the ohmic contact layer is less than or equal to 500 Å.

10. The display panel according to claim 7 , wherein the array substrate further comprises:
a passivation layer covering the source electrode, the drain electrode and the active layer, the passivation layer being provided with a via hole for exposing a portion of the drain electrode; and
a pixel electrode formed on one side of the passivation layer away from the source electrode, the pixel electrode being connected to the drain electrode through the via hole.

11. The display panel according to claim 8 , wherein the array substrate further comprises:
a passivation layer covering the source electrode, the drain electrode and the active layer, the passivation layer being provided with a via hole for exposing a portion of the drain electrode; and
a pixel electrode formed on one side of the passivation layer away from the source electrode, the pixel electrode being connected to the drain electrode through the via hole.

12. The display panel according to claim 9 , wherein the array substrate further comprises:
a passivation layer covering the source electrode, the drain electrode and the active layer, the passivation layer being provided with a via hole for exposing a portion of the drain electrode; and
a pixel electrode formed on one side of the passivation layer away from the source electrode, the pixel electrode being connected to the drain electrode through the via hole.

Assignees

• Shenzhen China Star Optoelect

Inventors

• Hu Xiaobo

Classifications

• G02F2201/501

  Blocking layers, e.g. against migration of ions · CPC title

• G02F1/1368

  in which the switching element is a three-electrode device {(G02F1/136277 takes precedence)} · CPC title

• G02F2202/10

  semiconductor · CPC title

• H01L27/127

  Electricity · mapped topic

• H01L29/66969

  Electricity · mapped topic