Manufacturing method of a thin film transistor

Patent metadata

Field	Value
Publication number	US-9312146-B2
Application number	US-201314354320-A
Country	US
Kind code	B2
Filing date	Oct 29, 2013
Priority date	Feb 19, 2013
Publication date	Apr 12, 2016
Grant date	Apr 12, 2016

Abstract

Embodiments of the invention provide a thin film transistor and a manufacturing method thereof and a display device. The thin film transistor includes a gate electrode, a gate insulation layer, an active layer, an ohmic contact layer, a source electrode and a drain electrode, and the source electrode and the drain electrode are connected to the active layer by the ohmic contact layer. The ohmic contact layer is provided at a lateral side of the active layer and contacts the lateral side of the active layer.

First claim

What is claimed is:

1. A manufacturing method of a thin film transistor, the thin film transistor comprising a gate electrode, a gate insulation layer, an active layer, an ohmic contact layer, a source electrode and a drain electrode,
wherein the method comprises: forming the ohmic contact layer by an injection process;
wherein the method comprises: forming a first groove and a second groove communicated with each other in the gate insulation layer; forming the active layer in the first groove: and forming the ohmic contact layer in the second groove by the injection process;
wherein a conductivity of the ohmic contact layer is not uniform, and the method comprises:
forming a photoresist layer on the gate insulation layer;
performing exposing and developing processes on the photoresist layer by using a multi-tone mask plate so as to form a photoresist-completely-removed region, a first to n-th photoresist-partially-retained regions and a photoresist-completely-retained region, wherein n is an integer equal to or greater than 2, thicknesses of the photoresist in the first to n-th photoresist-partially-retained regions are gradually increased, and the photoresist-completely-removed region corresponds to a region where the active layer is to be formed, the first to n-th photoresist-partially-retained regions correspond to a region where the ohmic contact layer is to be formed, and the photoresist-completely-retained region corresponds to other region;
etching the gate insulation layer in this photoresist-completely-removed region to form the first groove, and then forming the active layer in the first groove;
removing the photoresist in the first photoresist-partially-retained region and etching the gate insulation layer in this region to form a first portion of the second groove, and then forming a first sub-ohmic-contact-layer in the first portion of the second groove by using the injection process;
removing the photoresist in the second photoresist-partially-retained region and etching the gate insulation layer in this region to form a second portion of the second groove, and then forming a second sub-ohmic-contact-layer in the second portion of the second groove by using the injection process;
in the same way as that for forming the first sub-ohmic-contact-layer and the second sub-ohmic-contact-layer, forming other sub-ohmic-contact-layers until
removing the photoresist in the n-th photoresist-partially-retained region, etching the gate insulation layer in this region to form a n-th portion of the second groove and forming a n-th sub-ohmic-contact-layer in the n-th portion of the second groove by using the injection process; and
removing the photoresist in the photoresist-completely-retained region.

2. The manufacturing method of the thin film transistor according to claim 1 , wherein the first sub-ohmic-contact-layer, the second ohmic contact layer up to the n-th ohmic contact layer are provided in a same layer.

3. The manufacturing method of the thin film transistor according to claim 1 , wherein the first groove has a shape same as that of the active layer, and the second groove has a shape same as that of the ohmic contact layer.

4. The manufacturing method of the thin film transistor according to claim 1 , wherein the second groove is provided outside of the first groove.

5. The manufacturing method of the thin film transistor according to claim 1 , wherein the first groove and the second groove have a same depth.

6. The manufacturing method of the thin film transistor according to claim 1 , wherein the active layer and the ohmic contact layer are provided in a same layer.

7. The manufacturing method of the thin film transistor according to claim 1 , wherein the injection process is an inkjet printing process.

8. The manufacturing method of the thin film transistor according to claim 1 , wherein the active layer is formed by an injection process.

Assignees

• Boe Technology Group Co Ltd

Inventors

• Kong Xiangyong
• Cheng Jun
• Wang Dongfang
• Yuan Guangcai

Classifications

• H10P14/47 Primary

  Electrolytic deposition, i.e. electroplating; Electroless plating · CPC title

• H10D64/256

  for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies (source or drain electrodes of TFTs H10D30/673) · CPC title

• H10D30/6713

  characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes · CPC title

• H10D30/6711

  by using electrodes contacting the supplementary regions or layers · CPC title

• H10D30/6755 Primary

  Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate · CPC title