Processor that detects when system management mode attempts to reach program code outside of protected space

Patent metadata

Field	Value
Publication number	US-9448867-B2
Application number	US-201113997046-A
Country	US
Kind code	B2
Filing date	Dec 31, 2011
Priority date	Dec 31, 2011
Publication date	Sep 20, 2016
Grant date	Sep 20, 2016

Abstract

A method is described that includes detecting that a memory access of system management mode program code is attempting to reach program code outside of a protected region of memory by comparing a target memory address of a memory access instruction of the system management program code again information that defines confines of the protection region. The method also includes raising an error signal in response to the detecting.

First claim

What is claimed is:

1. A method, comprising:
detecting that a memory access of system management mode program code is attempting to reach program code outside of a protected region of memory by comparing a target memory address of a memory access instruction of said system management program code against information that defines confines of said protection region; and
raising an error signal in response to said detecting; and
not raising an error signal even though a second memory access instruction for program code targets memory space outside of said protected region because said second memory access instruction is being fetched as a consequence of speculation.

2. The method of claim 1 wherein said information is stored in control register space.

3. The method of claim 2 wherein said error signal includes setting a value in said control register space.

4. The method of claim 1 further comprising raising an error signal because said speculation is deemed to have been correct.

5. The method of claim 1 further comprising storing second information pertaining to said memory access instruction and storing an address where said second information is stored.

6. The method of claim 5 wherein said address is stored in control register space.

7. A semiconductor chip, comprising:
an instruction execution pipeline having logic circuitry to:
detect that a memory access of system management mode program code is attempting to reach program code outside of a protected region of memory by comparing a target memory address of a memory access instruction of said system management program code against information that defines confines of said protection region and raise an error signal in response to the detection, and
not raise an error signal even though a second memory access instruction for program code targets memory space outside of said protected region because said second memory access instruction is being fetched as a consequence of speculation.

8. The semiconductor chip of claim 7 wherein said logic circuitry is coupled to control register space that stores said information.

9. The semiconductor chip of claim 8 wherein said information defines a range of said protected region.

10. The semiconductor chip of claim 9 wherein said logic circuitry is part of hardware table walk logic circuitry within said memory unit.

11. The semiconductor chip of claim 7 wherein said logic circuitry is within a memory unit of said pipeline.

12. The semiconductor chip of claim 7 wherein said logic writes an error signal to control register space in response to detection that said memory access is attempting to reach said program code.

13. A computing system, comprising:
a processor having logic circuitry to
detect that a memory access of system management mode program code is attempting to reach program code outside of a protected region of memory by comparing a target memory address of a memory access instruction of said system management program code against information that defines confines of said protection region and raise an error signal in response to the detection, and
not raise an error signal even though a second memory access instruction for program code targets memory space outside of said protected region because said second memory access instruction is being fetched as a consequence of speculation; and

handler program code within said protected region of memory, said handler program code to read information descriptive of an error condition flagged by said logic circuitry.

14. The computing system of claim 13 , wherein said logic circuitry is coupled to control register space that stores said information.

15. The computing system of claim 14 , wherein said information defines a range of said protected region.

16. The computing system of claim 13 , wherein said logic circuitry is within a memory unit of said pipeline.

17. The computing system of claim 13 , wherein said logic circuitry is part of hardware table walk logic circuitry within said memory unit.

18. The computing system of claim 13 , wherein said logic writes an error signal to control register space in response to detection that said memory access is attempting to reach said program code.

Assignees

• Datta Shamanna M
• Parathasarathy Rajesh S
• Natu Mahesh S
• Binns Frank
• Kumar Mohan J
• Intel Corp

Inventors

• Datta Shamanna M
• Parathasarathy Rajesh S
• Natu Mahesh S
• Binns Frank
• Kumar Mohan J

Classifications

• G06F12/1441 Primary

  for a range · CPC title

• G06F11/0754 Primary

  by exceeding limits · CPC title

• G06F21/52

  during program execution, e.g. stack integrity {; Preventing unwanted data erasure; Buffer overflow} · CPC title