Signal path linearization

Patent metadata

Field	Value
Publication number	US-10340934-B1
Application number	US-201715845796-A
Country	US
Kind code	B1
Filing date	Dec 18, 2017
Priority date	Dec 18, 2017
Publication date	Jul 2, 2019
Grant date	Jul 2, 2019

Abstract

To address non-linearity, an on-chip linearization scheme is implemented along with an analog-to-digital converter (ADC) to measure and correct/tune for non-linearities and/or other non-idealities of the signal path having the ADC. The on-chip linearization scheme involves generating one or more test signals using an on-chip digital-to-analog converter (DAC) and providing the one or more test signals as input to the signal path to be linearized, and estimating non-linearity based on the one or more test signals and the output of the ADC. Test signals can include single-tone signals, multi-tone signals, and wideband signals spread over a range of frequencies. A time-delayed interleaving clocking scheme can be used to achieve a higher data rate for coefficient estimation without having to increase the sample rate of the ADC.

First claim

What is claimed is:

1. An integrated circuit having on-chip signal path linearization, the integrated circuit comprising:
a digital-to-analog converter for generating test signals;
a controller for providing a digital input signal to the digital-to-analog converter;
an analog-to-digital converter for receiving the test signals provided to a signal path and converting the test signals to a digital output signal; and
a processor for estimating coefficients corresponding to non-idealities of the signal path based the digital output signal resulting from the test signals;
wherein the test signals comprises tonal inputs having respective frequencies sweeping across one or more Nyquist zones of the analog-to-digital converter.

2. The integrated circuit of claim 1 , further comprising:
a first switch for disconnecting the signal path from receiving an external analog input during a calibration phase; and
a second switch for coupling an analog output of the digital-to-analog converter to the signal path during the calibration phase.

3. The integrated circuit of claim 1 , wherein the controller controls the digital-to-analog converter to generate single-tone signals as the test signals.

4. The integrated circuit of claim 1 , wherein the controller controls the digital-to-analog converter to generate multi-tone signals as the test signals.

5. The integrated circuit of claim 1 , wherein:
the respective frequencies are equally-spaced across the one or more Nyquist zones.

6. The integrated circuit of claim 1 , wherein:
the tonal inputs comprises a number of equally-spaced tones;
the digital output signal comprises a number of data sets generated from providing the equally-spaced tones to the signal path; and
the processor estimates the coefficients by relating a fundamental and a non-linear component in each one of the data sets and reconstructing a response corresponding to the non-idealities based on relationships between the fundamental and the non-linear component in each data set.

7. The integrated circuit of claim 1 , wherein the processor comprises digital hardware to implement some functions of the processor.

8. The integrated circuit of claim 1 , further comprising:
a summing node to allow test signals to be injected into the signal path.

9. The integrated circuit of claim 1 , wherein:
the digital output signal comprises a number of data sets generated from injecting tones to the signal path; and
the processor estimates the coefficients by relating a fundamental and a non-linear component in each one of the data sets.

10. The integrated circuit of claim 1 , wherein the digital-to-analog converter is provided in a same package as the analog-to-digital converter but not on a same semiconductor substrate as the analog-to-digital converter.

11. An integrated circuit having on-chip signal path linearization, the integrated circuit comprising:
a digital-to-analog converter;
a controller for providing a digital input signal to the digital-to-analog converter, wherein:
the controller comprises a pseudo-random number generator to generate the digital input signal; and
the controller controls the digital-to-analog converter to generate test signals comprising a wideband signal having a uniform, white frequency response across a range of frequencies;

an analog-to-digital converter for receiving the test signals provided to a signal path and converting the test signals to a digital output signal; and
a processor for estimating coefficients corresponding to non-idealities of the signal path based the digital output signal resulting from the test signals.

12. The integrated circuit of claim 11 , further comprising:
a buffer for capturing values of the digital output signal and/or values of a corrected digital output signal.

13. The integrated circuit of claim 11 , wherein:
the controller provides the same digital input signal during a first period and a second period; and
the controller, during the first period, generates a first clock signal for the digital-to-analog converter which is in phase with a clock signal driving the analog-to-digital converter, and during the second period, generates a second clock signal for the digital-to-analog converter which is out of phase with the clock signal driving the analog-to-digital converter.

14. The integrated circuit of claim 13 , further comprising:
a buffer to interleave, in memory locations of the buffer, values of the digital output signal generated based on the digital input signal being injected during the first period and values of the digital output signal generated based on the same digital input signal being injected during the second period, wherein the processor estimates the coefficients based on the values stored in the buffer.

15. The integrated circuit of claim 11 , wherein the processor comprises digital hardware to implement some functions of the processor.

16. The integrated circuit of claim 11 , wherein the digital-to-analog converter is provided in a same electronic package as the analog-to-digital converter but not on a same semiconductor substrate as the analog-to-digital converter.

17. A method for linearizing a signal path having an analog-to-digital converter, the method comprising:
generating, by a digital-to-analog converter on-chip with the analog-to-digital converter, a number of tonal inputs having input frequencies across a range of frequencies for injecting to the signal path;
capturing the same number of data sets of values of a digital output signal of the signal path generated based on the tonal inputs;
determining coefficients associated with non-idealities of the signal path based on the data sets; and
correcting for the non-idealities of the signal path using the coefficients.

18. The method of claim 17 , wherein generating the tonal inputs comprises generating one or more of: single-tone signal and multi-tone signal.

19. The method of claim 17 , further comprising:
capturing values of the digital output signal of the signal path and/or values of a corrected digital output signal in a buffer as the data sets.

20. The method of claim 17 , wherein determining coefficients comprises:
relating magnitude and phase of a fundamental and magnitude and phase of a non-linear component in each data set; and
extracting the non-idealities of the signal path based on relationships between the fundamental and the non-linear component determined from each data set.

21. The method of claim 17 , further comprising:
disconnecting the signal path from receiving an external analog input during a calibration phase; and
coupling an analog output of the digital-to-analog converter to the signal path during the calibration phase.

22. The method of claim 17 , wherein correcting for the non-idealities comprises:
writing coefficients to digital filters; and
filtering, by the digital filters, the digital output signal of the analog-to-digital converter.

23. The method of claim 17 , wherein correcting for the non-idealities comprises:
tuning analog circuitry in the signal path based on the coefficients.

24. The method of claim 17 , wherein determining the coefficients comprises:
determining a correction filter based on magnitude and phase information extracted from each one of the data set.

25. The method of claim 17 , wherein determining the coefficients comprises:
applying an inverse transformation to pairs of mag

Assignees

• Analog Devices Inc

Inventors

• Rakuljic Nevena
• Speir Carroll C
• Otte Eric
• Petersen Corey
• Bray Jeffrey P

Classifications

• H03M1/1042 Primary

  the look-up table containing corrected values for replacing the original digital values (H03M1/1052 takes precedence) · CPC title

• H03M1/1033 Primary

  over the full range of the converter, e.g. for correcting differential non-linearity · CPC title

• H03M1/1038

  by storing corrected or correction values in one or more digital look-up tables (H03M1/1057 takes precedence) · CPC title

• H03M1/1009

  Calibration · CPC title

• H03M1/12

  Analogue/digital converters ({H03M1/001 – } H03M1/10 take precedence) · CPC title