System and method for measuring the DC-transfer characteristic of an analog-to-digital converter

Patent metadata

Field	Value
Publication number	US-9584146-B2
Application number	US-201514886545-A
Country	US
Kind code	B2
Filing date	Oct 19, 2015
Priority date	Jan 16, 2015
Publication date	Feb 28, 2017
Grant date	Feb 28, 2017

Abstract

Systems and methods for measuring and compensating a DC-transfer characteristic of analog-to-digital converters are described. A test-signal generator comprising a sigma-delta modulator may provide calibration signals to an ADC. An output from the ADC may be filtered with a notch filter to suppress quantization noise at discrete frequencies introduced by the sigma-delta modulator. The resulting filtered signal may be compared against an input digital signal to the test-signal generator to determine a transfer characteristic of the ADC.

First claim

What is claimed is:

1. A calibration circuit for an analog-to-digital (ADC) converter, the calibration circuit comprising:
a test-signal generator comprising a first-order, digital, sigma-delta modulator that is configured to be connected to an analog input of the ADC;
a digital-to-analog converter (DAC) arranged to be coupled between an output of the test-signal generator and the analog input of the ADC; and
a digital filter connected to an output of the ADC, wherein the digital filter has attenuating notches at a plurality of frequencies that correspond to frequencies at which quantization noise tones are generated by the test-signal generator.

2. The calibration circuit of claim 1 , wherein the sigma-delta modulator is configured to produce an output signal that varies between only two signal levels and the DAC is configured to convert an input signal having only two signal levels.

3. The calibration circuit of claim 1 , wherein the ADC comprises a voltage-controlled-oscillator-based ADC.

4. The calibration circuit of claim 1 , wherein the ADC comprises a multi-bit sigma-delta modulator.

5. The calibration circuit of claim 1 , wherein a bit resolution of the ADC is any integer value from N=12 to N=24.

6. The calibration circuit of claim 1 , wherein the digital filter is a digital comb filter.

7. The calibration circuit of claim 1 , wherein the test-signal generator is configured to output a pulse-density modulated signal.

8. A calibration circuit for an analog-to-digital (ADC) converter, the calibration circuit comprising:
a test-signal generator configured to be connected to an analog input of the ADC;
a digital filter connected to an output of the ADC, wherein the digital filter has attenuating notches at a plurality of frequencies that correspond to frequencies at which quantization noise tones are generated by the test-signal generator; and
a low-pass filter arranged to be coupled between the output of the test-signal generator and the analog input to the ADC.

9. The calibration circuit of claim 6 , wherein the low-pass filter is an analog low-pass filter and has a cut-off frequency at a value approximately equal to or smaller than f clk/ 2M, where f clk is a clock frequency at which the test-signal generator is configured to operate and 2M+1 corresponds to a number of calibration measurements for the ADC.

10. The calibration circuit of claim 6 , wherein the low-pass filter is included in a transimpedance amplifier that is coupled to an input of the ADC, and the low-pass filter has a cut-off frequency at a value approximately equal to or greater than fclk/2M, where fclk is a clock frequency at which the test-signal generator is configured to operate and 2M+1 corresponds to a number of calibration measurements for the ADC.

11. The calibration circuit of claim 6 , wherein the low-pass filter attenuates at least some of the quantization noise tones by at least 2 dB.

12. A calibration circuit for an analog-to-digital (ADC) converter, the calibration circuit comprising:
a test-signal generator configured to be connected to an analog input of the ADC; and
a digital filter connected to an output of the ADC, wherein the digital filter has attenuating notches at a plurality of frequencies that correspond to frequencies at which quantization noise tones are generated by the test-signal generator, wherein the test-signal generator is configured to operate at a clock frequency f clk and the attenuating notches of the digital filter are located at integer multiples of f clk /2M where 2M+1 corresponds to a number of calibration measurements for the ADC.

13. A calibration circuit for an analog-to-digital (ADC) converter, the calibration circuit comprising:
a test-signal generator configured to be connected to an analog input of the ADC;
a digital filter connected to an output of the ADC, wherein the digital filter has attenuating notches at a plurality of frequencies that correspond to frequencies at which quantization noise tones are generated by the test-signal generator; and
a distortion corrector coupled to an output of the ADC, wherein the distortion corrector is configured to compensate for distortion introduced by the ADC,
wherein the distortion corrector comprises a look-up table and an interpolator.

14. The calibration circuit of claim 13 , wherein the interpolator is configured to receive values from the look-up table and compute an interpolated correction value that is used to correct a digital signal from the ADC, and wherein the computed interpolated correction value is based upon the received values from the look-up table.

15. The calibration circuit of claim 14 , wherein the distortion corrector is configured to select the received values from the look-up table based upon a portion of the digital signal received from the ADC to which the computed interpolated correction value is applied.

16. A method for calibrating an analog-to-digital converter (ADC), the method comprising:
applying a calibration signal from a test-signal generator to an analog input of the ADC; and
filtering an output digital signal from the ADC with a digital filter, wherein the digital filter has attenuating notches at a plurality of frequencies that correspond to frequencies at which quantization noise tones are generated by the test-signal generator.

17. The method of claim 16 , wherein the test-signal generator comprises a first-order, digital, sigma-delta modulator that outputs a signal having only two signal levels, and the method further comprises:
converting an output from the sigma-delta modulator with a two-level digital-to-analog converter (DAC) configured to receive only two input signal levels; and
low-pass filtering an output from the two-level DAC.

18. The method of claim 16 , further comprising:
applying a first calibration value to the input of the test-signal generator;
receiving a first output value from the ADC;
applying a reference value to the input of the test-signal generator;
receiving a reference output value from the ADC;
calculating a first difference value by taking a difference between the first output value and the reference output value; and
calibrating the ADC for the first calibration value based upon the first difference value.

19. The method of claim 18 , wherein the reference value corresponds to a value that is approximately at a middle of an input range for the ADC.

Assignees

• Mediatek Inc

Inventors

• Op 'T Eynde Frank
• Egan Nathan
• Muhammad Khurram
• Lo Tien-Yu
• Lo Chi-Lun
• Ashburn Michael A

Classifications

• H03M3/50

  Digital/analogue converters using delta-sigma modulation as an intermediate step (digital delta-sigma modulators per se H03M7/3004) · CPC title

• H03M1/1038

  by storing corrected or correction values in one or more digital look-up tables (H03M1/1057 takes precedence) · CPC title

• H03M1/109 Primary

  for DC performance, i.e. static testing (H03M1/1085 takes precedence) · CPC title

• H03M1/12

  Analogue/digital converters ({H03M1/001 – } H03M1/10 take precedence) · CPC title