Method of manufacturing finFETs with self-align contacts

Patent metadata

Field	Value
Publication number	US-10340348-B2
Application number	US-201615157274-A
Country	US
Kind code	B2
Filing date	May 17, 2016
Priority date	Nov 30, 2015
Publication date	Jul 2, 2019
Grant date	Jul 2, 2019

Abstract

A semiconductor device includes a fin structure, first and second gate structures, a source/drain region, a source/drain contact layer and a separation layer. The fin structure protrudes from an isolation insulating layer disposed over a substrate and extends in a first direction. The first and second gate structures are formed over the fin structure and extend in a second direction crossing the first direction. The source/drain region is disposed between the first and second gate structures. The interlayer insulating layer is disposed over the fin structure, the first and second gate structures and the source/drain region. The first source/drain contact layer is disposed on the first source/drain region. The separation layer is disposed adjacent to the first source/drain contact layer. Ends of the first and second gate structures and an end of the source drain contact layer are in contact with a same face of the separation layer.

First claim

What is claimed is:

1. A method of manufacturing a semiconductor device, comprising:
forming a first fin structure and a second fin structure over a substrate, the first and second fin structures extending in a first direction and being arranged in a second direction crossing the first direction, the first fin structure being arranged in parallel with the second fin structure;
forming an isolation insulating layer over the substrate such that upper portions of the first and second fin structures are exposed from the isolation insulating layer;
forming a first gate structure and a second gate structure over parts of the first and second fin structures, the first and second gate structures extending in the second direction and being arranged in the first direction in parallel with each other;
forming an interlayer dielectric layer made of a silicon oxide based material on the first and second gate structures and over the first and second fin structures;
forming a first mask pattern having a first opening over the interlayer dielectric layer, the first opening being located above the first and second gate structures; and
cutting the first and second gate structures through the first opening of the first mask pattern, wherein:
the method further comprises:
etching the isolation insulating layer and the interlayer dielectric layer through the first opening so as to form a first recess;
forming an insulating layer in the first recess;
forming a second mask pattern having a second opening so as to expose a part of the insulating layer in the first recess and a part of the interlayer dielectric layer;
etching the exposed part of the interlayer dielectric layer through the second opening so as to form a second recess; and
forming a conductive material in the second recess, and

the second mask pattern has a third opening so as to expose a part of the insulating layer outside the first recess,
in the etching the exposed part of the interlayer dielectric layer through the second opening, the part of the insulating layer outside the first recess is etched so as to form a third recess, and
in the forming the conductive material in the second recess, the conductive material is also formed in the third recess.

2. The method of claim 1 , wherein the etching the isolation insulating layer and the interlayer dielectric layer is performed during the cutting the first and second gate structures.

3. The method of claim 1 , wherein the insulating layer includes SiN.

4. The method of claim 1 , wherein the conductive material includes at least one of W, Co, Ni, Ti, and Ta, a silicide thereof and a nitride thereof.

5. The method of claim 1 , wherein the first opening extends in the second direction and the second opening extends in the first direction.

6. The method of claim 1 , wherein:
the second opening is located above either one of the first and second fin structures, and
the conductive material formed in the second recess is in contact with the either one of the first and second fin structures.

7. The method of claim 1 , wherein:
the second opening is located above the first and second fin structures, and
the conductive material formed in the second recess is in contact with the first and second fin structures.

8. The method of claim 1 , further comprising forming a conductive plug over the separation insulating layer, the conductive material formed in the second recess and the conductive material formed in the third recess, thereby electrically connecting the conductive material formed in the second recess and the conductive material formed in the third recess.

9. A method of manufacturing a semiconductor device, comprising:
forming an underlying structure, the underlying structure including:
a first pair of two gate structures and a second pair of two gate structures;
a separation insulating layer separating the first pair of two gate structures and the second pair of two gate structures; and
an interlayer dielectric layer in which the first and second pairs of two gate structures are embedded;

forming a mask pattern having an opening, the opening being disposed over the separation insulating layer, a part of the interlayer dielectric layer between two gate structures of the second pair of two gate structures and over a part of the interlayer dielectric layer between two gate structures of the first pair of two gate structures;
etching the exposed the part of the interlayer dielectric layer through the opening, thereby forming a first recess; and
forming a conductive material in the first recess, thereby forming a contact layer.

10. The method of claim 9 , wherein:
an end of the contact layer is in contact with the separation insulating layer, and
the separation insulating layer is made of an insulating material different from the interlayer dielectric layer.

11. The method of claim 9 , wherein the contact layer includes at least one of W, Co, Ni, Ti, and Ta, a silicide thereof and a nitride thereof.

12. The method of claim 9 , wherein the separation insulating layer is made of SiN.

13. The method of claim 9 , further comprising forming a conductive plug on the separation insulating layer and the contact layer.

14. The method of claim 9 , wherein:
the separation insulating layer extends in a first direction,
the first pair of two gate structures extend in a second direction and the two gate structures of the first pair of two gate structures are arranged in parallel with each other in the first direction, the second direction crossing the first direction, and
the second pair of two gate structures extend in the second direction and the two gate structures of the second pair of two gate structures are arranged in parallel with each other in the first direction.

15. The method of claim 9 , wherein the underlying structure is formed by:
forming an isolation insulating layer over a substrate;
forming a first gate structure and a second gate structure over the isolation insulating layer;
forming the interlayer dielectric layer over the first and second gate structures;
cutting the first and second gate structures by lithography and etching operations, thereby forming the first and second pairs of two gate structures;
etching the isolation insulating layer and the interlayer dielectric layer, thereby forming a second recess; and
forming an insulating layer in the second recess, thereby forming the separation insulating layer.

16. The method of claim 15 , wherein ends of the first and second pairs of two gate structures are in contact with the separation insulating layer.

17. A method of manufacturing a semiconductor device, comprising:
forming an underlying structure, the underlying structure including:
a first pair of two gate structures and a second pair of two gate structures;
a separation insulating layer separating the first pair of two gate structures and the second pair of two gate structures; and
an interlayer dielectric layer in which the first and second pairs of two gate structures are embedded;

forming a first mask pattern having a first opening and a second opening, the first opening being disposed over a part of the interlayer dielectric layer between two gate structures of the second pair of two gate structures, and the first opening being disposed over a part of the interlayer dielectric layer between two gate structures of the first pair of two gate structures;
etching the exposed the part of the interlayer dielectric layer through the first opening and the second opening, thereby forming a first recess and a second rece

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Huang Yi-Jyun
• Hsieh Tung-Heng
• Young Bao-Ru

Classifications

• H10P50/282

  of inorganic materials · CPC title

• H10P14/69433

  the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz · CPC title

• H10P14/69215

  the material being a silicon oxide, e.g. SiO2 · CPC title

• H10D64/01354

  passivation or protection of the electrode, e.g. using re-oxidation · CPC title

• H10W20/0698

  Local interconnections · CPC title