Wiring structure for trench fuse component with methods of fabrication

Patent metadata

Field	Value
Publication number	US-9431339-B2
Application number	US-201414184003-A
Country	US
Kind code	B2
Filing date	Feb 19, 2014
Priority date	Feb 19, 2014
Publication date	Aug 30, 2016
Grant date	Aug 30, 2016

Abstract

The present disclosure generally relates to a wiring structure for a fuse component and corresponding methods of fabrication. A wiring structure for a fuse component according to the present disclosure can include: a first electrical terminal embedded within a doped conductive layer, the doped conductive layer being positioned between two insulator layers of an integrated circuit (IC) structure; a dielectric liner positioned between the first electrical terminal and the doped conductive layer; a second electrical terminal embedded within the doped conductive layer; wherein each of the first electrical terminal and the second electrical terminal are further embedded in one of the two insulator layers, and the dielectric liner is configured to degrade upon becoming electrically charged.

First claim

What is claimed is:

1. A method of fabricating a trench fuse component, the method comprising:
forming a first insulator layer between a doped conductive layer and an oppositely doped substrate of an integrated circuit (IC) structure, such that no p-n junction exists between the oppositely doped substrate and the doped conductive layer;
forming a first electrical terminal within the doped conductive layer, wherein the first electrical terminal includes a dielectric liner thereon;
forming a second electrical terminal within the doped conductive layer; and
coupling one of a source terminal and a drain terminal of a transistor to one of the first electrical terminal and the second electrical terminal.

2. The method of claim 1 , further comprising forming a silicide region to directly couple one of the source terminal and the drain terminal of the transistor to one of the first electrical terminal and the second electrical terminal.

3. The method of claim 1 , further comprising:
forming a second insulator layer adjacent to the doped conductive layer, wherein each of the first electrical terminal and the second electrical terminal are at least partially embedded within the second insulator layer.

4. The method of claim 3 , further comprising:
forming an interlayer dielectric over the second insulator layer, wherein the second electrical terminal is at least partially embedded within the interlayer dielectric; and
forming an electrical contact within the interlayer dielectric, wherein the formed electrical contact is electrically coupled to the second electrical terminal.

5. The method of claim 1 , further comprising:
forming a doped conductive material within each of the first electrical terminal and the second electrical terminal, wherein each of the doped conductive material and the doped conductive layer have a common polarity.

6. The method of claim 5 , wherein one of the doped conductive material and the doped conductive layer includes one of polysilicon and silicon germanium.

7. The method of claim 1 , further comprising forming an isolation ring to enclose a cross sectional area of the doped conductive layer, the first electrical terminal, and the second electrical terminal.

8. A method of fabricating a trench fuse component, the method comprising:
forming a first insulator layer between a doped conductive layer and an oppositely doped substrate of an integrated circuit (IC) structure, such that no p-n junction exists between the oppositely doped substrate and the doped conductive layer;
forming a first electrical terminal within the doped conductive layer, wherein the first electrical terminal includes a dielectric liner thereon;
forming a second electrical terminal within the doped conductive layer;
forming a second insulator layer adjacent to the doped conductive layer, wherein each of the first electrical terminal and the second electrical terminal are at least partially embedded within the second insulator layer;
forming an interlayer dielectric adjacent over the second insulator layer, wherein the second electrical terminal is at least partially embedded within the interlayer dielectric; and
forming an electrical contact within the interlayer dielectric, wherein the formed electrical contact is electrically coupled to the second electrical terminal.

9. The method of claim 8 , further comprising coupling one of a source terminal and a drain terminal of a transistor to one of the first electrical terminal and the second electrical terminal.

10. The method of claim 8 , further comprising forming a coupling silicide region to directly couple one of a source terminal and a drain terminal of a transistor to one of the first electrical terminal and the second electrical terminal.

11. The method of claim 8 , further comprising:
forming a doped conductive material within each of the first electrical terminal and the second electrical terminal, wherein each of the doped conductive material and the doped conductive layer have a common polarity.

12. The method of claim 11 , wherein one of the doped conductive material and the doped conductive layer includes one of polysilicon and silicon germanium.

13. The method of claim 8 , further comprising forming an isolation ring to enclose a cross sectional area of the doped conductive layer, the first electrical terminal, and the second electrical terminal.

14. A method of fabricating a trench fuse component, the method comprising:
forming a first insulator layer between a doped conductive layer and an oppositely doped substrate of an integrated circuit (IC) structure, such that no p-n junction exists between the oppositely doped substrate and the doped conductive layer;
forming a first electrical terminal within the doped conductive layer, wherein the first electrical terminal includes a dielectric liner thereon;
forming a second electrical terminal within the doped conductive layer; and
forming a doped conductive material within each of the first electrical terminal and the second electrical terminal, wherein each of the doped conductive material and the doped conductive layer have a common polarity.

15. The method of claim 14 , further comprising coupling one of a source terminal and a drain terminal of a transistor to one of the first electrical terminal and the second electrical terminal.

16. The method of claim 14 , further comprising forming a silicide region to directly couple one of a source terminal and a drain terminal of a transistor to one of the first electrical terminal and the second electrical terminal.

17. The method of claim 14 , wherein one of the doped conductive material and the doped conductive layer includes one of polysilicon and silicon germanium.

18. The method of claim 14 , further comprising forming an isolation ring to enclose a cross sectional area of the doped conductive layer, the first electrical terminal, and the second electrical terminal.

19. The method of claim 14 , further comprising:
forming a second insulator layer adjacent to the doped conductive layer, wherein each of the first electrical terminal and the second electrical terminal are at least partially embedded within the second insulator layer.

20. The method of claim 19 , further comprising:
forming an interlayer dielectric over the second insulator layer, wherein the second electrical terminal is at least partially embedded within the interlayer dielectric; and
forming an electrical contact within the interlayer dielectric, wherein the formed electrical contact is electrically coupled to the second electrical terminal.

Assignees

• IBM

Inventors

• Kirihata Toshiaki
• Maciejewski Edward P
• Iyer Subramanian S
• Pei Chengwen
• Wehella-Gamage Deepal U

Classifications

• H10W20/491

  Antifuses, i.e. interconnections changeable from non-conductive to conductive · CPC title

• H10W20/064

  by modifying the conductivity of conductive parts, e.g. by alloying · CPC title

• H10W20/49

  Adaptable interconnections, e.g. fuses or antifuses · CPC title

• H10W20/021

  of interconnections within wafers or substrates · CPC title

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title