Semiconductor device having a plurality of fins and method for fabricating the same

Patent metadata

Field	Value
Publication number	US-9659932-B2
Application number	US-201615197243-A
Country	US
Kind code	B2
Filing date	Jun 29, 2016
Priority date	Jan 29, 2015
Publication date	May 23, 2017
Grant date	May 23, 2017

Abstract

A semiconductor device having a plurality of fins including at least one first fin and at least one second fin formed on a semiconductor substrate is provided. Each of the first fin and second fin has a first portion and a second portion. A gate electrode structure overlies the first portion of the plurality of fins. The gate electrode structure includes a gate electrode, and a gate dielectric layer between the gate electrode and the plurality of fins, A first electrode overlies the second portion of the plurality of fins and the first electrode is in electrical contact with the second portion of the plurality of fins. The gate electrode structure is in direct physical contact with the first portion of the first fin and the gate electrode structure is spaced apart from the first portion of the second fin.

First claim

What is claimed is:

1. A method for fabricating a semiconductor device comprising:
patterning a semiconductor substrate to form a plurality of fins including at least one first fin and at least one second fin, wherein each of the first fin and second fin comprise a first portion and a second portion;
etching the first portion of the second fin to form a recess in the second fin;
forming a gate electrode structure overlying the first portion of the plurality of fins, the gate electrode structure comprising a gate electrode, and a gate dielectric layer between the gate electrode and the plurality of fins, wherein the gate electrode structure is in direct physical contact with the first portion of the first fin and the gate electrode structure is spaced apart from the first portion of the second fin; and
forming a first electrode overlying the second portion of the plurality of fins, wherein the first electrode is in electrical contact with the second portion of the plurality of fins.

2. The method according to claim 1 , further comprising forming a mask over the plurality of fins prior to etching the second fin.

3. The method according to claim 1 , further comprising depositing a first insulating material in regions between the plurality of fins.

4. The method according to claim 3 , further comprising depositing a second insulating material over the first insulating material and plurality of fins after forming the gate electrode structure.

5. The method according to claim 4 , further comprising:
patterning the second insulating material to form an opening exposing the second portion of the plurality of fins; and
depositing a conductive material in the opening to form the first electrode.

6. The method according to claim 1 further comprising forming source/drain regions on the second portion of the plurality of fins between the second portion of the plurality of fins and the first electrode.

7. The method according to claim 6 , wherein source/drain regions formed on adjacent fins are in direct physical contact.

8. A method for fabricating a semiconductor device comprising:
forming a plurality of fins, including at least one first fin and at least one second fin on a semiconductor substrate, wherein each of the first fin and second fin comprise a first portion and a second portion;
depositing a first insulating material in regions between the plurality of fins;
forming a mask over the plurality of fins after depositing the first insulating material;
forming a recess in the first portion of the second fin after forming the mask;
forming a gate electrode structure overlying the first portion of the plurality of fins, the gate electrode structure comprising a gate electrode, and a gate dielectric layer between the gate electrode and the plurality of fins, wherein the gate electrode structure is in direct physical contact with the first portion of the first fin and the gate electrode structure is spaced apart from the first portion of the second fin; and
depositing a second insulating material over the first insulating material and plurality of fins after forming the gate electrode structure.

9. The method according to claim 8 , further comprising:
forming a first electrode overlying the second portion of the plurality of fins, wherein the first electrode is in electrical contact with the second portion of the plurality of fins.

10. The method according to claim 8 , further comprising:
patterning the second insulating material to form an opening exposing the second portion of the plurality of fins; and
depositing a conductive material in the opening to form a first electrode overlying the second portion of the plurality of fins, wherein the first electrode is in electrical contact with the second portion of the plurality of fins.

11. The method according to claim 10 , further comprising forming source/drain regions on the second portion of the plurality of fins between the second portion of the plurality of fins and the first electrode.

12. The method according to claim 10 , wherein source/drain regions formed on adjacent fins are in direct physical contact.

13. A method for fabricating a semiconductor device comprising:
patterning a semiconductor substrate to form an array of fins comprising a plurality of active fins and a plurality of dummy fins extending along a first direction, wherein each of the active fins and the dummy fins extend along a second direction substantially perpendicular to the first direction, and a plurality of dummy fins are located at each end region of the array in the first direction, wherein each fin includes a first portion and a pair of second portions located on opposing sides of the first portion;
forming a recess in the first portion of each of the dummy fins;
forming a gate electrode structure overlying the first portion of each of the fins in the array of fins, the gate electrode structure comprising a gate electrode, and a gate dielectric layer between the gate electrode and the plurality of fins, wherein the gate electrode structure is in contact with the first portions of the active fins and the gate electrode structure is not in contact with the first portions of the dummy fins; and
forming a first electrode overlying one of the second portions of each of the fins in the array of fins, wherein the first electrode is in contact with one of the second portions of each of the active fins and the dummy fins.

14. The method according to claim 13 , further comprising forming a second electrode overlying another of the second portions of each of the fins in the array of fins, wherein the second electrode is located on an opposing side of the gate electrode structure from the first electrode, and the second electrode is in contact with the another of the second portions of each of the active fins and the dummy fins.

15. The method according to claim 13 , further comprising forming source/drain regions at each of the second portions of each of the fins in the array of fins before forming the first electrode.

16. The method according to claim 15 , further comprising removing the gate electrode structure after forming the source/drain regions, and forming a high k dielectric layer and a metal gate electrode in a region where the gate electrode structure was removed.

17. The method according to claim 13 , further comprising forming a photoresist mask over the array of fins prior to forming the recess in each of the dummy fins.

18. The method according to claim 17 , further comprising forming a filler material over the array of fins prior to forming the photoresist mask.

19. The method according to claim 18 , further comprising removing the photoresist mask and the filler material after forming the recess in each of the dummy fins.

20. The method according to claim 13 , further comprising forming an insulating material over the array fins after forming the recess in each of the dummy fins.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Huang Yu-Lien

Classifications

• H10P95/064

  the removal being chemical etching · CPC title

• H10P50/691

  for Group V materials or Group III-V materials · CPC title

• H10P50/642

  Chemical etching · CPC title

• H01L29/785

  Electricity · mapped topic

• H01L27/0886 Primary

  Electricity · mapped topic