Off-axis epitaxial lift off process

Patent metadata

Field	Value
Publication number	US-10337087-B2
Application number	US-201815876001-A
Country	US
Kind code	B2
Filing date	Jan 19, 2018
Priority date	Aug 15, 2011
Publication date	Jul 2, 2019
Grant date	Jul 2, 2019

Abstract

Embodiments described herein provide processes for forming and removing epitaxial films and materials from growth wafers by epitaxial lift off (ELO) processes. In some embodiments, the growth wafer has edge surfaces with an off-axis orientation which is utilized during the ELO process. The off-axis orientation of the edge surface provides an additional variable for controlling the etch rate during the ELO process and therefore the etch front may be modulated to prevent the formation of high stress points which reduces or prevents stressing and cracking the epitaxial film stack. In one embodiment, the growth wafer is rectangular and has an edge surface with an off-axis orientation rotated by an angle greater than 0° and up to 90° relative to an edge orientation of <110> at 0°.

First claim

We claim:

1. A method for forming an epitaxial film stack during an epitaxial lift off process, the method comprising:
providing a growth wafer diced from a crystalline wafer, the growth wafer having a plurality of edge surfaces, wherein none of the plurality of edge surfaces of the growth wafer has an orientation that is perpendicular to a crystallographic orientation of a flat cut of the crystalline wafer, and wherein none of the plurality of edge surfaces of the growth wafer has an orientation that is parallel to the crystallographic orientation of the flat cut of the crystalline wafer;
growing a sacrificial layer over the growth wafer;
forming the epitaxial film stack over the sacrificial layer; and
removing the sacrificial layer by an etching process, the etching process including a first etch rate of the sacrificial layer near corners of the plurality of edge surfaces that is different than a second etch rate of the sacrificial layer near sides of the plurality of edge surfaces.

2. The method of claim 1 , wherein the orientation of each of the edge surfaces includes an off-axis orientation that is at an angle greater than 0° and less than 90° with respect to the crystallographic orientation of the flat cut of the crystalline wafer, the crystallographic orientation being a <110> crystal lattice orientation.

3. The method of claim 1 , wherein the etching process is a lateral etching process that produces an etch front of a wet etch solution that encompasses the sacrificial layer at an interface of the wet etch solution and the sacrificial layer.

4. The method of claim 3 , wherein the etch front forms substantially octagonal geometry comprising alternating sides of a plurality of side edge fronts and corner edge fronts.

5. The method of claim 4 , wherein the corner edge fronts advance at the first etch rate of the sacrificial layer near the corners of the plurality of edge surfaces and the side edge fronts advance at the second etch rate of the sacrificial layer near the sides of the plurality of edge surfaces.

6. The method of claim 4 , wherein the plurality of side edge fronts and corner edge fronts converge at a center of the sacrificial layer at a same time to complete the removal of the sacrificial layer.

7. The method of claim 3 , further comprising:
separating the epitaxial film stack from the growth wafer after removal of the sacrificial layer, wherein the geometry of the etch front of the sacrificial layer transitions during the epitaxial lift off process from a substantially rectangular geometry, to a substantially octagonal geometry, and then to a substantially rounded geometry.

8. The method of claim 3 , wherein the sacrificial layer has a rectangular geometry and comprises side edges and corners prior to being exposed to the wet etch solution.

9. The method of claim 1 , wherein the growth wafer is diced from the crystalline wafer at an angle that is 45° and corresponds to an off-axis orientation of the growth wafer relative to the crystalline wafer.

10. The method of claim 1 , wherein the first etch rate is 1.4 times the second etch rate.

11. The method of claim 1 , wherein the first etch rate is faster than the second etch rate.

12. The method of claim 1 , wherein each edge surface of the growth wafer is oriented in a direction other than that of a cleavage plane associated with the flat cut of the crystalline wafer that is indicative of the crystallographic orientation of the crystalline wafer.

13. The method of claim 1 , wherein the crystalline wafer from which the growth wafer is diced is a gallium arsenide (GaAs) wafer.

Assignees

• Alta Devices Inc

Inventors

• Gmitter Thomas
• He Gang
• Archer Melissa
• Neo Siew

Classifications

• C30B29/40

  AIIIBV compounds {wherein A is B, Al, Ga, In or Tl and B is N, P, As, Sb or Bi} · CPC title

• C30B33/06

  Joining of crystals · CPC title

• C30B33/10

  in solutions or melts · CPC title

• C30B33/08

  Etching · CPC title

• C30B29/42

  Gallium arsenide · CPC title