Power switching circuitry including power-up control

Patent metadata

Field	Value
Publication number	US-10333379-B2
Application number	US-201615382076-A
Country	US
Kind code	B2
Filing date	Dec 16, 2016
Priority date	Dec 16, 2016
Publication date	Jun 25, 2019
Grant date	Jun 25, 2019

Abstract

Some embodiments include apparatuses and methods using the apparatuses. One of the apparatuses includes a first power supply node, a second power supply node, transistors coupled in parallel between the first and second power supply nodes, and a controller to provide a first voltage, a second voltage, and a third voltage to gates of the transistors based on digital information. The first, second, and third voltages have different values based on values of the digital information.

First claim

What is claimed is:

1. An apparatus comprising:
a first power supply node;
a second power supply node;
transistors coupled in parallel between the first and second power supply nodes;
a controller to provide a first voltage, a second voltage, and a third voltage to gates of the transistors based on digital information, the first, second, and third voltages having different values based on values of the digital information;
first additional transistors coupled in parallel between the first and second power supply nodes; and
first buffers coupled in series with an output of the controller, each of the first buffers including an output node coupled to a gate of one of the first additional transistors.

2. The apparatus of claim 1 , further comprising:
second additional transistors coupled in parallel between the first and second power supply nodes; and
second buffers coupled in series with the output of the controller in parallel with the first buffers, each of the second buffers including an output node coupled to a gate of one of the second additional transistors.

3. An apparatus comprising:
a first power supply node;
a second power supply node;
transistors coupled in parallel between the first and second power supply nodes; and
a controller to provide a first voltage, a second voltage, and a third voltage to gates of the transistors based on digital information, the first, second, and third voltages having different values based on values of the digital information, wherein in the controller includes a generator to generate the first, second, and third voltages, and a selector to receive the digital information and select the first, second, and third voltages provided to the gates of the transistors based on different values of the digital information.

4. The apparatus of claim 3 , wherein the second power supply node is coupled to a functional unit, and the controller is to provide the first, second, and third voltages to the gates of the transistors when the functional unit changes from a first power consumption state to a second power consumption state.

5. The apparatus of claim 4 , wherein the transistors are to turn off during the first power consumption state and to turn on in the second power consumption state.

6. The apparatus of claim 4 , wherein the first power consumption state includes a sleep mode of the functional unit.

7. An apparatus comprising:
a first power supply node;
a second power supply node;
transistors coupled in parallel between the first and second power supply nodes; and
a controller to provide a first voltage, a second voltage, and a third voltage to gates of the transistors based on digital information, the first, second, and third voltages having different values based on values of the digital information, wherein the controller includes a resistive network coupled to the first power supply node and a ground node, the resistive network including a first node to provide the first voltage, a second node to provide the second voltage, and a third node to provide the third voltage.

8. The apparatus of claim 7 , wherein the controller includes a selector including input nodes coupled to respective first, second, and third nodes of the resistive network, an output node coupled to the gates of the transistors, and nodes to receive bits of the digital information.

9. The apparatus of claim 8 , wherein the selector includes first, second, and third transmission gates coupled to the first, second, and third nodes, respectively, of the resistive network.

10. An apparatus comprising:
an integrated circuit die;
a voltage regulator located on the integrated circuit die and coupled to a first power supply node; and
power switching circuitry located on the integrated circuit die and coupled to the first power supply node and a second power supply node, the power switching circuitry including:
transistors coupled in parallel between the first and second power supply nodes;
a controller to provide a first voltage, a second voltage, and a third voltage to gates of the transistors based on digital information, the first, second, and third voltages having different values based on values of the digital information;
first additional transistors coupled in parallel between the first and second power supply nodes; and
a first circuit path coupled to a node of the controller to propagate a signal from the node of the controller to gates of the first additional transistors.

11. The apparatus of claim 10 , further comprising:
second additional transistors coupled in parallel between the first and second power supply nodes; and
a second circuit path different from the first circuit path, the second circuit path coupled to the node of the controller to propagate the signal from the node of the controller to gates of the second additional transistors.

12. The apparatus of claim 11 , wherein each of the first and second circuit paths includes buffers coupled in series.

13. The apparatus of claim 10 , wherein the controller is to provide a first digital value of the digital information, a second digital value of the digital information, and third digital value of the digital information, and the values of the first, second, and third voltages are based on respective first, second, and third values of the digital information.

14. The apparatus of claim 10 , wherein the second power supply node is coupled to a functional unit, and the controller is to provide the first, second, and third voltages to the gates of the transistors when the functional unit changes from a lower power consumption state to a higher power consumption state.

15. The apparatus of claim 10 , further comprising a power delivery path to couple to a battery, wherein the voltage regulator includes an input node coupled to the power delivery path.

16. The apparatus of claim 10 , wherein the integrated circuit die includes a processor.

17. The apparatus of claim 10 , further comprising an antenna coupled to the integrated circuit die.

18. A method comprising:
providing first, second, and third digital information to a controller located on an integrated circuit die, the controller coupled to transistors located on the integrated circuit die, the transistors coupled in parallel between a first power supply node and a second power supply node;
applying a first voltage to gates of the transistors based on the first digital information;
applying a second voltage to the gates of the transistors based on the second digital information;
applying a third voltage to the gates of the transistors based on the third digital information;
selecting the first voltage from a resistive ladder network based on the first digital information;
selecting the second voltage from the resistive ladder network based on the second digital information; and
selecting the third voltage from the resistive ladder network based on the third digital information.

19. The method of claim 18 , wherein the first voltage has a first value, the second voltage has a second value, the third voltage has a third value, the first value is greater than the second value, and the second value is greater than the third value.

20. The method of claim 19 , wherein the first voltage is applied to the gates of the transistors before the second voltage is applied to the gates of the transistors, and the second voltage is applied to the gates of the transistors before the third voltage is applied to the gates of the transistors.

21. A method compris

Assignees

• Intel Corp

Inventors

• Sutanthavibul Suphachai Chai
• Rajwani Iqbal
• Thaploo Anupama A
• Tallapragada Surya Sasi Kiran
• Bhatt Daivik H
• Jiang Lei
• Kim Stephen
• Meinerzhagen Pascal A
• Khellah Muhammad M

Classifications

• H03K2217/0036

  Means reducing energy consumption · CPC title

• H03K19/0013

  in field effect transistor circuits · CPC title

• Y02B70/1491

  Cross-Sectional Technologies · mapped topic

• H02M2001/0032

  Electricity · mapped topic

• H03K17/6871

  the output circuit comprising more than one controlled field-effect transistor · CPC title