Apparatus and method for reducing di/dt during power wake-up

Patent metadata

Field	Value
Publication number	US-9755631-B2
Application number	US-201514951343-A
Country	US
Kind code	B2
Filing date	Nov 24, 2015
Priority date	Nov 24, 2015
Publication date	Sep 5, 2017
Grant date	Sep 5, 2017

Abstract

Described is an apparatus which comprises: a power gate transistor coupled to an ungated power supply node and a gated power supply node, the power gate transistor having a gate terminal; a resistive device; a first transistor coupled in series with the resistive device together forming a pair, the first transistor also coupled to the gate terminal of the power gate transistor; a capacitive device coupled in parallel to the series coupled pair of the first transistor and resistive device; and a second transistor coupled to the gate terminal of the power gate transistor and the ungated power supply node.

First claim

We claim:

1. An apparatus comprising:
a power gate transistor coupled to an ungated power supply node and a gated power supply node, the power gate transistor having a gate terminal;
a resistive device;
a first transistor coupled in series with the resistive device and together forming a pair, the first transistor also connected to the gate terminal of the power gate transistor;
a capacitive device coupled in parallel to the series coupled pair of the first transistor and resistive device; and
a second transistor coupled to the gate terminal of the power gate transistor and the ungated power supply node.

2. The apparatus of claim 1 , wherein the second transistor is operable to charge the gate terminal of the power gate transistor during a low power mode.

3. The apparatus of claim 2 , wherein the first transistor is operable to discharge the gate terminal of the power gate transistor when the low power mode is exited.

4. The apparatus of claim 1 , wherein the power gate is a p-type transistor, wherein the first transistor is an n-type transistor, and wherein the second transistor is a p-type transistor.

5. The apparatus of claim 1 , wherein the first and second transistors are controllable by a low power mode exit signal.

6. The apparatus of claim 1 , wherein the power gate transistor is a primary power gate which is coupled in parallel to a secondary power gate, and wherein the secondary power gate is larger in size than the primary power gate.

7. The apparatus of claim 6 , wherein the secondary power gate is operable to turn on after the primary power gate is to turn on.

8. The apparatus of claim 1 further comprising an inverter having an input coupled to the gate terminal of the power gate transistor and an output to control a first transistor of a power gate control circuitry.

9. The apparatus of claim 1 comprises:
a second resistor;
a third transistor coupled in series with the second resistor, wherein the third transistor is coupled to the gate terminal of the power gate transistor; and
a pulse generator having:
an input coupled to the gate terminal of the power gate transistor; and
an output coupled to a gate terminal of the third transistor.

10. The apparatus of claim 9 , wherein third transistor is an n-type transistor.

11. The apparatus of claim 9 , wherein the pulse generator comprises a low threshold inverter and a high threshold inverter.

12. The apparatus of claim 9 , wherein the pulse generator comprises a low threshold Schmitt Trigger and a high threshold Schmitt Trigger.

13. The apparatus of claim 1 comprises:
a second resistor;
a third transistor coupled in series with the second resistor, wherein the third transistor is coupled to the gate terminal of the power gate transistor; and
an inverter having an input coupled to the gate terminal of the power gate and an output coupled to a gate terminal of the third transistor.

14. An apparatus comprising:
a first modular primary power gate; and
a second modular primary power gate coupled in a sequence with the first modular primary power gate, wherein the second modular primary power gate is to turn on after the first modular primary power gate is to turn on, wherein at least one of the first and second modular primary power gates includes:
a power gate transistor coupled to an ungated power supply node and a gated power supply node, the power gate transistor having a gate terminal;
a resistive device;
a first transistor coupled in series with the resistive device together forming a pair, the first transistor also connected to the gate terminal of the power gate transistor;
a capacitive device coupled in parallel to the series coupled pair of the first transistor and resistive device; and
a second transistor coupled to the gate terminal of the power gate transistor and the ungated power supply node.

15. The apparatus of claim 14 comprises:
a third modular primary power gate coupled in a sequence with the second modular primary power gate; and
a fourth modular primary power gate coupled in a sequence with the second modular primary power gate,
wherein the third and fourth modular primary power gates are to turn on after the second modular primary power gate is to turn on.

16. The apparatus of claim 14 , wherein at least one of the third and fourth modular primary power gates include:
a power gate transistor coupled to an ungated power supply node and a gated power supply node, the power gate transistor having a gate terminal;
a resistive device;
a first transistor coupled in series with the resistive device and together forming a pair, the first transistor also coupled to the gate terminal of the power gate transistor;
a capacitive device coupled in parallel to the series coupled pair of the first transistor and resistive device; and
a second transistor coupled to the gate terminal of the power gate transistor and the ungated power supply node.

17. A system comprising:
a memory;
a processor coupled to the memory, the processor including an apparatus which includes:
a power gate transistor coupled to an ungated power supply node and a gated power supply node, the power gate transistor having a gate terminal;
a resistive device;
a first transistor coupled in series with the resistive device together forming a pair, the first transistor also connected to the gate terminal of the power gate transistor;
a capacitive device coupled in parallel to the series coupled pair of the first transistor and resistive device; and
a second transistor coupled to the gate terminal of the power gate transistor and the ungated power supply node; and

a wireless interface for allowing the processor to communicate with another device.

18. The system of claim 17 , wherein the second transistor is operable to charge the gate terminal of the power gate transistor during a low power mode.

19. The system of claim 18 , wherein the first transistor is operable to discharge the gate terminal of the power gate transistor when the low power mode is exited.

20. The system of claim 17 , wherein the power gate transistor is a p-type transistor, wherein the first transistor is an n-type transistor, and wherein the second transistor is a p-type transistor.

Assignees

• Intel Corp

Inventors

• Shim Yong
• Kulkarni Jaydeep P
• Meinerzhagen Pascal A
• Khellah Muhammad M

Classifications

• H03K17/145

  in field-effect transistor switches · CPC title

• H03K17/08104 Primary

  in field-effect transistor switches (H03K17/0812, H03K17/0814 take precedence) · CPC title

• H03K3/0377

  Bistables with hysteresis, e.g. Schmitt trigger (non-regenerative amplitude discriminators G01R19/165) · CPC title

• H03K19/0016 Primary

  by using a control or a clock signal, e.g. in order to apply power supply · CPC title