Quantization noise cancellation in a feedback loop

Patent metadata

Field	Value
Publication number	US-10327659-B2
Application number	US-201715621621-A
Country	US
Kind code	B2
Filing date	Jun 13, 2017
Priority date	Nov 13, 2016
Publication date	Jun 25, 2019
Grant date	Jun 25, 2019

Abstract

An analog front end (AFE) system for substantially eliminating quantization error or noise can combine an input of an integrator circuit in the AFE system with an input of the digital-to-analog converter (DAC) circuit in the feedback loop of the AFE system. By combining the input of the integrator with the input of the DAC circuit in the feedback loop, the in-band quantization noise of the filter can be substantially eliminated, thereby improving measurement accuracy.

First claim

What is claimed is:

1. An analog front end (AFE) system for compensating quantization error, the AFE system comprising:
a gain circuit including a first input configured to receive an input signal, a second input configured to receive a feedback signal using a feedback path, and an output configured to provide an amplified version of the difference between the input signal and the feedback signal;
an analog-to-digital converter (ADC) configured to receive a gain circuit output signal and output a digital output signal;
a digital frequency-selective filter circuit configured to receive the ADC digital output signal and output a quantized filter circuit output signal;
a digital-to-analog converter (DAC) circuit, the DAC circuit configured to receive the filter output signal and output the feedback signal to the second input of the gain circuit; and
an AFE system output circuit configured to combine the ADC output signal and the filter circuit output signal, and output a quantization error-compensated AFE output signal.

2. The AFE system of claim 1 , wherein the gain circuit output is configured to be periodically sampled to substantially reject any sampling noise contribution of the gain circuit.

3. The AFE system of claim 1 , wherein the gain circuit comprises capacitive gain-setting elements.

4. The AFE system of claim 1 , wherein the digital frequency-selective filter includes a quantizer circuit to output the quantized filter circuit output signal.

5. The ATE system of claim 4 , wherein the quantizer circuit includes a sigma-delta circuit.

6. The AFE system of claim 4 , wherein the quantizer circuit receives a filtered signal having a first number of bits, and wherein the quantized filter circuit output signal has a second number of bits less than the first number of bits.

7. The AFE system of claim 1 , wherein the ADC includes a sigma-delta ADC circuit.

8. The AFE system of claim 1 , wherein the ADC includes a successive approximation register (SAR) ADC circuit.

9. The AFE, system of claim 1 , DAC circuit is configured to perform dynamic element matching.

10. The AFE system of claim 1 , wherein the gain circuit includes a capacitive gain amplifier (CGA) circuit.

11. The AFE system of claim 1 , wherein the digital frequency-selective filter circuit includes an integrator.

12. The AFE system of claim 1 , where the digital frequency-selective filter circuit includes a low-pass filter circuit.

13. A method of analog-to-digital conversion that compensates for a quantization error component of the conversion, the method comprising:
receiving an analog input signal for conversion into a digital output signal;
combining the analog input signal with a feedback signal to create difference signal;
amplifying the difference signal;
performing an analog-to-digital conversion on the amplified signal to create a converted digital signal;
filtering the converted digital signal to generate a filtered signal with quantization error;
performing a digital-to-analog conversion on the filtered signal to generate the feedback signal; and
combining the converted digital signal with the filtered signal to generate a system output in which the quantization error component is substantially reduced.

14. The method of claim 13 , wherein performing an analog-to-digital conversion on the amplified signal includes:
performing an analog-to-digital conversion using a sigma-delta converter on the amplified signal to create a converted digital signal.

15. The method of claim 13 , wherein performing an analog-to-digital conversion on the amplified signal includes:
performing an analog-to-digital conversion using a successive-approximation-register (SA) converter on the amplified signal to create a converted digital signal.

16. The method of claim 13 , wherein filtering the converted digital signal to generate a filtered signal with quantization error includes:
filtering the converted digital signal and then quantizing the result.

17. The method of claim 16 , wherein quantizing the result includes:
quantizing the result using a noise-shaping quantizer circuit.

18. The method of claim 13 , filtering the converted digital signal to generate a filtered signal with quantization error includes:
using a frequency-selective filter including an integrator.

19. The method of claim 13 , filtering the converted digital signal to generate a filtered signal with quantization error includes:
using a frequency-selective filter including a low-pass filter.

20. An electrocardiogram (ECG) measurement circuit comprising:
an analog front end (AFE) system for compensating quantization error, the AFE system including:
a gain circuit including a first input configured to receive an input signal and a second input configured to receive a feedback signal using a feedback path;
an ADC circuit configured to receive a gain circuit output signal and output an ADC circuit output signal;
a frequency-selective filter circuit configured to receive the ADC circuit output signal and output a filter circuit output signal;
a quantizer circuit, the quantizer circuit configured to receive the filter circuit output signal and output a quantized signal;
a digital-to-analog converter (DAC) circuit, the DAC circuit configured to receive the quantized signal and output the feedback signal to the second input of the gain circuit; and
an AFE system output circuit configured to combine the ADC circuit output signal and the quantized signal and output a quantization error-compensated AFE output signal.

21. The ECG measurement circuit of claim 20 , wherein the gain circuit output is configured to be periodically sampled to substantially reject any sampling noise contribution of the gain circuit.

22. The ECG measurement circuit of claim 20 , wherein the digital frequency-selective filter includes a quantizer circuit to output the quantized filter circuit output signal.

23. The ECG measurement circuit of claim 22 , wherein the quantizer circuit includes a sigma-delta circuit.

24. The ECG measurement circuit of claim 22 , wherein the quantizer circuit receives a filtered signal having a first number of bits, and wherein the quantized filter circuit output signal has a second number of bits less than the first number of bits.

Assignees

• Analog Devices Inc

Inventors

• Kalb Arthur J
• Sharma Yogesh Jayaraman
• Shu Marvin Liu

Classifications

• A61B5/308

  for electrocardiography [ECG] · CPC title

• A61B5/305

  Common mode rejection · CPC title

• A61B5/304

  Switching circuits · CPC title

• A61B5/7203 Primary

  for noise prevention, reduction or removal · CPC title

• H03M3/46

  using a combination of at least one delta-sigma modulator in series with at least one analogue/digital converter of a different type · CPC title