ADC with capacitive difference circuit and digital sigma-delta feedback

Patent metadata

Field	Value
Publication number	US-10135459-B2
Application number	US-201615334011-A
Country	US
Kind code	B2
Filing date	Oct 25, 2016
Priority date	Oct 25, 2016
Publication date	Nov 20, 2018
Grant date	Nov 20, 2018

Abstract

A low power high precision mixed signal analog to digital converter is provided for processing biometric signals in the presence of a large interferer signal for cableless patient monitoring; a capacitive difference circuit produces an analog difference signal by differencing an analog feedback loop signal and an input signal; an analog-to-digital converter sigma delta converter produces a digital version of the difference signal, a digital feedback loop includes a digital integrator and a capacitive digital-to-analog converter configured to produce the analog loop feedback signal based upon the digital version of the difference.

First claim

The invention claimed is:

1. A low power analog-to-digital converter system comprising:
a capacitive difference circuit, coupled to receive an analog input signal and to receive an analog loop feedback signal, and to output an analog difference signal representing a difference between the analog input signal and the analog loop feedback signal;
a capacitive difference amplifier circuit configured to amplify the analog difference signal in proportion to a ratio of a first capacitance of the capacitive difference circuit and a second capacitance of the capacitive difference circuit to provide an amplified analog difference signal;
a sigma-delta analog-to-digital converter (SD-ADC) coupled to produce a digital output signal based upon the amplified analog difference signal;
a digital integrator circuit, coupled to receive the digital output signal and to provide a digital integration signal; and
a capacitive digital-to-analog converter (DAC) coupled to produce the analog loop feedback signal based upon the digital output signal.

2. The system of claim 1 ,
wherein the analog input signal includes a biometric signal portion within a first frequency range and includes an interferer signal portion within a second frequency range; and
wherein the analog loop feedback signal includes a signal portion within the second frequency range.

3. The system of claim 1 ,
wherein the analog input signal includes a biometric signal portion within a first higher frequency range and includes an interferer signal portion within a second lower frequency range; and
wherein the digital integrator is configured to pass a portion of the digital output signal in the second lower frequency range and to block a portion of the digital output signal in the first higher frequency range.

4. The system of claim 1 ,
wherein the analog input signal includes an ECG signal portion within a higher first frequency range and includes an interferer signal portion within a lower second frequency range; and
wherein the analog loop feedback signal includes a signal portion within the lower second frequency range.

5. The system of claim 1 ,
wherein the analog input signal includes a biometric signal portion within a first frequency range and includes an interferer signal portion within a second frequency range; and
wherein the analog loop feedback signal includes a signal portion within the second frequency range.

6. The system of claim 5 ,
wherein the digital integrator is configured to pass a portion of the digital output signal in the second frequency range and to block a portion of the digital output signal in the first frequency range.

7. The system of claim 5 ,
wherein the digital integrator is configured to pass a digital output signal in both the first and second frequency range.

8. The system of claim 1 ,
wherein the analog input signal includes an ECG signal portion within a frequency range of approximately 50 mHz to 150 Hz and has a maximum amplitude of about +/−10 mV and includes an interferer signal portion within a frequency range of approximately DC to 50 mhz and has a maximum amplitude larger than +/−1V; and
wherein the digital integrator amplifies a component of the digital output signal in the approximately DC to 50 mHz frequency range to an amplitude level of the component of the interferer signal portion.

9. The system of claim 1 ,
wherein the digital integrator includes a summation circuit; and
wherein a bandwidth of the summation circuit can be changed by changing a co-efficient of the summation circuit to change the bandwidth of the feedback loop.

10. The system of claim 1 ,
wherein the digital integrator includes a summation circuit; and further followed by:
a quantizer circuit coupled to quantize a digital integrator signal and to provide the quantized digital integrator signal to the capacitive DAC.

11. The system of claim 1 ,
wherein the digital integrator includes a summation circuit; and further followed by:
a digital sigma delta quantizer coupled to quantize a digital integrator signal and to provide the quantized digital integrator signal to the capacitive DAC.

12. The system of claim 1 ,
wherein the capacitive DAC includes circuitry configured to use oversampling to minimize an effect of a capacitor mismatch.

13. The system of claim 1 ,
wherein the capacitive DAC includes circuitry configured to use a dynamic elements matching technique to shape an effect of a capacitor mismatch.

14. The system of claim 1 ,
wherein the capacitive difference circuit includes first capacitor coupled to receive charge proportional to the input signal and a second capacitor coupled to receive charge proportional to the loop feedback signal.

15. A low power analog-to-digital converter system comprising:
a capacitive difference circuit that includes a first capacitor coupled to receive charge proportional to an input signal and a second capacitor coupled to receive charge proportional to an analog loop feedback signal and to provide an analog difference signal proportional to a ratio of capacitances of the first capacitor and the second capacitor;
a capacitive difference amplifier circuit that includes an amplifier circuit and a third capacitor configured to amplify the analog difference signal in proportion to a ratio of capacitances of the third capacitor and the first capacitor and to provide an amplified version of the analog difference signal;
a sigma-delta analog-to-digital converter (SD-ADC) coupled to produce a digital output signal based upon the amplified analog difference signal;
a digital integrator circuit, coupled to receive the digital output signal and to provide a digital integration signal; and
a capacitive digital-to-analog converter (DAC) coupled to produce the analog loop feedback signal based upon the digital integration signal.

16. The system of claim 15 , wherein the capacitive difference amplifier is configured to chop the input signal, the analog loop feedback signal, and the amplified analog difference signal to eliminate 1/f noise of the capacitive difference amplifier in a frequency range of interest.

17. The system of claim 15 , wherein the second capacitor is a component of the capacitive DAC.

18. The system of claim 15 , wherein the capacitive DAC includes an array of unit capacitors coupled in parallel to be selectively switchable between a first reference voltage and a second reference voltage to act as the second capacitor.

19. A method for converting a low power analog input signal to a digital output signal, the method comprising:
producing an analog difference signal representing a difference between the analog input signal and an analog loop feedback signal;
amplifying the analog difference signal in proportion to a ratio of a first capacitance and a second capacitance to generate an amplified analog difference signal;
producing a digital output signal, by a sigma-delta analog-to-digital converter (SD-ADC), based at least in part on the amplified analog difference signal;
integrating the digital output signal to generate a digital integration signal; and
producing the analog loop feedback signal based at least in part on the digital integration signal.

20. A low power digital-to-analog converter system, comprising:
means for producing an analog difference signal representing a difference between an analog input signal and an analog loop feedback signal;
means for amplifying the analog difference signal in proportion to a ratio of a first capacitance and a se

Assignees

• Sharma Yogesh Jayaraman
• Kalb Arthur J
• Analog Devices Inc

Inventors

• Sharma Yogesh Jayaraman
• Kalb Arthur J

Classifications

• A61B5/7203

  for noise prevention, reduction or removal · CPC title

• H03M3/496

  Details of sampling arrangements or methods · CPC title

• H03M3/458 Primary

  Analogue/digital converters using delta-sigma modulation as an intermediate step · CPC title

• H03M3/464 Primary

  Details of the digital/analogue conversion in the feedback path · CPC title

• H03M3/422

  having one quantiser only · CPC title