Apparatus and method for temperature compensated gain and mismatch trim in subranging quantizers and analog to digital converters

Patent metadata

Field	Value
Publication number	US-9214950-B1
Application number	US-201514694428-A
Country	US
Kind code	B1
Filing date	Apr 23, 2015
Priority date	Apr 23, 2015
Publication date	Dec 15, 2015
Grant date	Dec 15, 2015

Abstract

A flash analog to digital converter (ADC) provides a temperature compensated trim current by applying a first temperature compensated reference current across a replica resistor ladder. The reference current is mirrored to a trim digital to analog converter, which outputs a fractional portion of the temperature compensated reference current. The proportional trim current is then fed back to the reference current to provide a trimmed temperature compensated reference current. The trimmed reference current is mirrored across the output resistor ladder providing a trimmed current in which the trim varies along with temperature changes due to the trim current being a proportion of the temperature compensated reference current. A proportional trim current which varies with temperature changes is applied to the gain current trim and mismatch current trim in a DAC of a quantizing stage of a sub-ranging ADC.

First claim

What is claimed is:

1. An analog to digital converter (ADC) for providing a temperature compensated reference current to an output resistor ladder comprising:
an operational amplifier (opamp) having a first voltage input and a second voltage input, said opamp configured to output a modulated output signal based on a differential voltage between said first and second voltage inputs;
a first current source coupled to a replica resistor ladder, said replica resistor ladder being a replica of said output resistor ladder, said first current source configured to receive said modulated output signal and to output an adjusted reference current responsive to said modulated output signal;
a second current source configured to mirror said adjusted reference current;
a trim digital to analog converter (DAC) coupled to said second current source, said trim DAC configured to receive the mirrored adjusted reference current and to output a trim current that represents a percentage of said mirrored adjusted reference current, wherein said trim current is combined with said adjusted reference current across said replica resistor ladder at a feedback node between said first current source and said replica resistor ladder to produce a voltage level at said feedback node, said voltage level being fed back to one of said first and second inputs of said operational amplifier; and
a temperature independent reference voltage source that is provided to the other of said first and second input of said operational amplifier that does not receive said feedback node voltage level.

2. The ADC of claim 1 , wherein the modulated output signal is representative of a change in temperature based on a change in resistance of said replica resistor ladder.

3. The ADC of claim 1 , further comprising:
an output current source coupled to said output resistor ladder and configured to mirror said adjusted reference current across said output resistor ladder.

4. The ADC of claim 3 , wherein said output resistor ladder comprises:
a first plurality of series connected resistors connected at a first end to said third current source and configured to receive a first input of a differential input signal at a first input node located between two of said first plurality of series connected resistors;
a second plurality of series connected resistors connected at a first end to said third current source and configured to receive a second input of said differential input signal at a second input node located between two of said second plurality of series connected resistors.

5. The ADC of claim 4 , wherein said replica resistor ladder is a replica of one of said first plurality of series connected resistors and said second plurality of series connected resistors.

6. The ADC of claim 5 , further comprising:
a plurality of comparator circuits, each comparator circuit of said plurality of comparator circuits associated with a node located between two adjacent resistors in said first plurality of series connected resistors, and a corresponding node between two adjacent resistors of said second plurality of series connected resistors.

7. The ADC of claim 6 , wherein each of said plurality of comparator circuits is configured to:
compare a first voltage at said associated node located between two adjacent resistors of said first plurality of series connected resistors, and a second voltage at said associated node located between two adjacent resistors of said second plurality of series connected resistors and based on said comparison;
output a first output value if said first voltage is greater than said second voltage; and
output a second output value if said first voltage is less than or equal to said second voltage.

8. The ADC of claim 7 , further comprising a plurality of latch circuits, each latch circuit of said plurality of latch circuits corresponding to one of said plurality of comparator circuits, each latch circuit configured to receive the output value of said corresponding comparator circuit and to maintain said comparator output value for a predetermined time.

9. The ADC of claim 1 , wherein said first input of said opamp is an inverting input, and said second input of said opamp is a non-inverting input, and said opamp is configured to produce a modulated output signal, that when applied to said first current source, produces said adjusted reference current that generates a voltage level at said feedback node which maintains a zero voltage differential across said first and second inputs of said opamp.

10. The ADC of claim 1 , further comprising:
a second operational amplifier (opamp) having a first voltage input and a second voltage input, said second opamp configured to output a modulated output signal based on a differential voltage between said first and second voltage inputs of said second operational amplifier;
a third current source coupled to said replica resistor ladder at an end opposing said first current source, said replica resistor ladder being a replica of said output resistor ladder, and said third current source configured to receive said modulated output signal of said second operational amplifier and to output a second adjusted reference current responsive to said modulated output signal of said second operational amplifier;
a fourth current source configured to mirror said second adjusted reference current;
a second trim DAC coupled to said fourth current source, said second trim DAC configured to receive the mirrored adjusted reference current and to output a second trim current that represents a percentage of said mirrored second adjusted reference current, wherein said second trim current is combined with said second adjusted reference current across said replica resistor ladder at a second feedback node between said third current source and said second end of said replica resistor ladder producing a second voltage level at said second feedback node said second voltage level being fed back to the one of said first and second inputs of said second operational amplifier; and
a second temperature independent reference voltage source that is provided to the other of said first and second input of said second operational amplifier that does not receive said second feedback node voltage level.

11. The ADC of claim 10 , further comprising:
a first output current source connected to said output resistor ladder at a second end opposite a second output current source, said first output current source configured to mirror said second adjusted reference current.

12. The ADC of claim 11 , further comprising:
a third temperature independent reference voltage source connected to a third input node located between two adjacent resistors of said replica resistor ladder.

13. A temperature compensated digital to analog converter (DAC) comprising:
an input for receiving a digital input signal;
an output for outputting a voltage representative of said digital input signal;
an output resistor connected between said input and said output;
an array of unit cells configured to create a current through said output resistor representative of said digital input signal;
a current gain control circuit comprising:
at least one replica unit cell configured to draw a temperature compensated reference current across at least one replica resistor, the at least one replica resistor configured to replicate said output resistor of the temperature compensated DAC, wherein said at least one replica unit cell is connected to a plurality of output unit cells for producing an output voltage level across said output resistor;
a trim DAC connected to the at least one replica cell, the trim DAC conf

Assignees

• Lockheed Corp

Inventors

• Davis Brandon R
• Omori Toshi
• Linder Lloyd F
• Pereira Victoria T

Classifications

• H03M1/089 Primary

  of temperature variations · CPC title

• H03M1/00

  Analogue/digital conversion; Digital/analogue conversion (conversion of analogue values to or from differential modulation H03M3/00) · CPC title

• H03M1/001

  Analogue/digital/analogue conversion · CPC title

• H03M1/12

  Analogue/digital converters ({H03M1/001 – } H03M1/10 take precedence) · CPC title

• H03M1/365

  the voltage divider being a single resistor string · CPC title