Wide-range local oscillator (LO) generators and apparatuses including the same

Patent metadata

Field	Value
Publication number	US-10326460-B2
Application number	US-201815869437-A
Country	US
Kind code	B2
Filing date	Jan 12, 2018
Priority date	Jan 19, 2017
Publication date	Jun 18, 2019
Grant date	Jun 18, 2019

Abstract

A local oscillator generator (LO generator) may be configured to transmit an LO signal to a mixer. The LO generator may include an input buffer configured to generate a first internal oscillator signal based on the input oscillator signal. The LO generator may include a frequency dividing circuit configured to generate a second internal oscillator signal based on dividing a frequency of the first internal oscillator signal. The LO generator may include an output buffer configured to generate the LO signal based on the second internal oscillator signal. The input buffer and the frequency dividing circuit may each be configured to receive a power voltage independently of the output buffer.

First claim

What is claimed is:

1. A local oscillator generator (LO generator) configured to transmit an LO signal to a mixer, the LO generator comprising:
an input buffer configured to generate a first internal oscillator signal based on an input oscillator signal;
a frequency dividing circuit configured to generate a second internal oscillator signal based on dividing a frequency of the first internal oscillator signal; and
an output buffer configured to generate the LO signal based on the second internal oscillator signal,
wherein the input buffer and the frequency dividing circuit are each configured to receive a power voltage independently of the output buffer,
wherein the frequency dividing circuit includes
a plurality of first frequency dividers configured to mutually independently divide the frequency of the first internal oscillator signal and generate separate, respective output signals of a plurality of output signals, and
a selection circuit configured to selectively output one output signal of the plurality of output signals of the plurality of first frequency dividers as the second internal oscillator signal,

wherein the selection circuit includes at least one 2:1 multiplexer disposed in a hierarchical fashion.

2. The LO generator of claim 1 , wherein the input buffer and the frequency dividing circuit are further configured to mutually independently receive power voltages, respectively.

3. The LO generator of claim 1 , wherein the output buffer includes an AC-coupled buffer, the AC-coupled buffer configured to AC-couple the second internal oscillator signal.

4. The LO generator of claim 3 , wherein the AC-coupled buffer includes
an inverter;
a feedback resistor having two ends connected to an input terminal of the inverter and an output terminal of the inverter, respectively; and
a capacitor having a first end and a second end, the first end configured to receive the second internal oscillator signal, the second end connected to the input terminal of the inverter.

5. The LO generator of claim 3 , wherein
the second internal oscillator signal has a duty cycle of 50%, and
the output buffer further includes a duty adjustment circuit, the duty adjustment circuit configured to generate the LO signal such that the LO signal has a duty cycle of 25% from an output signal of the AC-coupled buffer.

6. The LO generator of claim 1 , wherein the input buffer and the frequency dividing circuit are further configured to receive a variable power voltage, respectively.

7. The LO generator of claim 1 , wherein the at least one 2:1 multiplexer includes two gated inverters.

8. The LO generator of claim 1 , wherein the frequency dividing circuit further includes at least one first switch, the at least one first switch configured to cut off power that is supplied to at least one first frequency divider of the plurality of first frequency dividers.

9. The LO generator of claim 1 , wherein the at least one 2:1 multiplexer includes a plurality of 2:1 multiplexers, and the selection circuit further includes at least one second frequency divider, the at least one second frequency divider connected between at least two 2:1 multiplexers of the plurality of 2:1 multiplexers.

10. The LO generator of claim 9 , wherein the selection circuit further includes at least one second switch, the at least one second switch configured to cut off power that is supplied to the at least one second frequency divider.

11. The LO generator of claim 1 , wherein
at least one first frequency divider of the plurality of first frequency dividers includes an injection-locked oscillator, the injection-locked oscillator including a plurality of gated inverters, the injection-locked oscillator including a sequence of stages, each stage including at least two gated inverters of the plurality of gated inverters,
each gated inverter of the plurality of gated inverters includes first and second PMOS transistors and first and second NMOS transistors connected in series sequentially between a positive power voltage and a negative power voltage,
the at least one first frequency divider is configured to generate, in a given stage of the sequence of stages, an input signal of a next stage in a plurality of drains of a second PMOS transistor and a first NMOS transistor of a gate inverter of the given stage, respectively,
the at least one first frequency divider is configured to apply, in the given stage of the sequence of stages, an output signal of a previous stage to a plurality of gates of a first PMOS transistor and a second NMOS transistor of the gate inverter of the given stage, respectively, and
the at least one first frequency divider is configured to apply the first internal oscillator signal to a plurality of gates of the second PMOS transistor and the first NMOS transistor of the gate inverter of the given stage, respectively.

12. The LO generator of claim 11 , wherein each transistor of the first and second PMOS transistors and the first and second NMOS transistors is a fin field-effect transistor (FinFET).

13. The LO generator of claim 11 , wherein the at least one first frequency divider is configured to divide a frequency of the first internal oscillator signal at a frequency division ratio of (2n+1), wherein a value of n is 1 or a prime number.

14. An apparatus for wireless communication, the apparatus comprising:
a local oscillator generator (LO generator) configured to generate a first internal oscillator signal based on an input oscillator signal, generate a second internal oscillator signal based on dividing a frequency of the first internal oscillator signal, and generate an LO signal based on the second internal oscillator signal, the LO generator further configured to receive a first power voltage;
a mixer configured to receive the LO signal; and
a controller configured to control the frequency of the input oscillator signal and a frequency division ratio of the LO generator based on a carrier frequency of the wireless communication, the controller further configured to control the first power voltage based on the frequency of the input oscillator signal and the frequency division ratio of the LO generator,
wherein the LO generator includes a frequency dividing circuit configured to generate the second internal oscillator signal based on dividing the frequency of the first internal oscillator signal,
wherein the frequency dividing circuit includes
a plurality of first frequency dividers configured to mutually independently divide the frequency of the first internal oscillator signal and generate separate, respective output signals of a plurality of output signals, and
a selection circuit configured to selectively output one output signal of the plurality of output signals of the plurality of first frequency dividers as the second internal oscillator signal,
wherein the selection circuit includes at least one 2:1 multiplexer disposed in a hierarchical fashion.

15. The apparatus of claim 14 , wherein the LO generator includes
an input buffer configured to generate the first internal oscillator signal based on the input oscillator signal; and
an output buffer configured to generate the LO signal based on the second internal oscillator signal,
wherein the frequency dividing circuit is further configured to receive the first power voltage, and the output buffer includes an AC-coupled buffer, the AC-coupled buffer configured to receive a second power voltage and AC-couple the second internal oscillator signal.

16. The apparatus of claim 15 , wherein
the input buffer is further configured to receive a third

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Nam-Seog
• Ko Sang-Soo
• Kang Byoung-Joong

Classifications

• H03L7/101

  using an additional control signal to the controlled loop oscillator derived from a signal generated in the loop (H03L7/113, H03L7/187 take precedence) · CPC title

• H03K5/1565

  the output pulses having a constant duty cycle · CPC title

• H03L7/0992

  comprising a counter or a frequency divider · CPC title

• H03L7/00

  Automatic control of frequency or phase; Synchronisation · CPC title

• H03K21/026

  comprising logic circuits · CPC title