Complex-pole load offering concurrent image rejection and channel selection

US9479140B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9479140-B2
Application numberUS-201414255094-A
CountryUS
Kind codeB2
Filing dateApr 17, 2014
Priority dateApr 16, 2014
Publication dateOct 25, 2016
Grant dateOct 25, 2016

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

A complex-pole load is configured as a parallel circuit, having 4 transistors arranged in pairs. Each pair of transistors has a transistor gated by a control voltage sources, and connected in parallel with a transistor diode connected for gating by the respective input. The control voltage sources result in the circuit synthesizing a first order complex pole at a positive IF (+IF) or a negative IF (−IF) for channel selection and image rejection, offering image rejection and channel selection concurrently.

First claim

Opening claim text (preview).

What is claimed is: 1. A complex pole load comprising: a parallel circuit comprising 8 transistors arranged in four pairs, with each pair receiving filtered output currents from a biquad filter circuit as an input to conduct I and Q current, respectively, in the pairs, each pair of transistors comprising a transistor in one pair gated by control voltage sources, connected in parallel with a transistor diode connected for gating by the respective input of a transistor in the other pair, and the control voltage sources comprising complex voltage components, with an I channel driven by Q channel IF signals, and a Q channel driven by I channel IF signals, resulting in the circuit synthesizing a first order complex pole load at a positive IF (+IF) or a negative IF (IF) for channel selection and image rejection, offering image rejection and channel selection concurrently. 2. The IF-noise-shaping transistorized current-mode lowpass filter of claim 1 , further comprising: a second set of circuit elements, thereby separately applying the pole loads to I and Q complex signals.

Assignees

Inventors

Classifications

  • by tuning the receiver frequency · CPC title

  • Amplitude regulation arrangements · CPC title

  • using adaptive balancing or compensation means (adaptive filter circuits and algorithms H03H) · CPC title

  • with field-effect devices (H03F3/195 takes precedence) · CPC title

  • Services using short range communication, e.g. near-field communication [NFC], radio-frequency identification [RFID] or low energy communication · CPC title

Patent family

Related publications grouped by family.

External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US9479140B2 cover?
A complex-pole load is configured as a parallel circuit, having 4 transistors arranged in pairs. Each pair of transistors has a transistor gated by a control voltage sources, and connected in parallel with a transistor diode connected for gating by the respective input. The control voltage sources result in the circuit synthesizing a first order complex pole at a positive IF (+IF) or a negative…
Who is the assignee on this patent?
Univ Macau
What technology area does this patent fall under?
Primary CPC classification H03H11/1213. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Oct 25 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).