Multi-stage frequency dividers having duty cycle correction circuits therein

Patent metadata

Field	Value
Publication number	US-9543960-B1
Application number	US-201514966913-A
Country	US
Kind code	B1
Filing date	Dec 11, 2015
Priority date	Jul 28, 2015
Publication date	Jan 10, 2017
Grant date	Jan 10, 2017

Abstract

A multi-stage frequency divider includes a cascaded arrangement of first and second integer dividers configured to collectively divide a frequency of a periodic reference signal by an integer amount equal to a product of (2N+1) and (2M+1), where N and M are unequal positive integers greater than two. A duty cycle enhancement circuit is provided, which is synchronized to the periodic reference signal and configured to generate a periodic signal having 2MN+N+M cycles of high followed by 2MN+N+M+1 cycles of low or vice versa, where a duration of each cycle is equivalent to a period of the periodic reference signal. A duty cycle correction circuit is provided as a final stage and is configured to generate a periodic output signal having a uniform duty cycle from the periodic signal generated by the duty cycle enhancement circuit.

First claim

That which is claimed is:

1. A multi-stage frequency divider, comprising:
a divider circuit responsive to a periodic reference signal to be divided, said divider circuit having at least first and second integer dividers therein, which are electrically coupled in a cascaded arrangement so that the second integer divider receives, at an input thereof, an intermediate divider signal derived from a first output of the first integer divider;
a duty cycle enhancement circuit configured to generate an intermediate output signal having an N/N+1 duty cycle in response to at least first and second output signals generated by said divider circuit, where: (i) N is a positive integer and 2N+1 equals a product of a first divide value of the first integer divider and a second divide value of the second integer divider, and (ii) at least one of the first and second output signals has a duty cycle less than the N/N+1 duty cycle; and
a duty cycle correction circuit configured to generate a periodic output signal having a uniform duty cycle and a period equal to the product times a period of the periodic reference signal, in response to the intermediate output signal having the N/N+1 duty cycle.

2. The multi-stage frequency divider of claim 1 , wherein said divider circuit comprises a first retimer circuit configured to generate the intermediate divider signal by adjusting a phase of a periodic signal generated at the first output of the first integer divider.

3. The multi-stage frequency divider of claim 2 , wherein the first retimer circuit is responsive to the periodic reference signal.

4. The multi-stage frequency divider of claim 1 , wherein said duty cycle enhancement circuit and said duty cycle correction circuit are configured to collectively support generation of the periodic output signal having a uniform duty cycle when the first and second integer dividers are both supporting respective odd integer frequency division therein.

5. The multi-stage frequency divider of claim 1 , wherein said duty cycle enhancement circuit is responsive to the periodic reference signal and is configured to delay an output signal generated by the second integer divider by M cycles of the periodic reference signal, where M is a positive integer and 2M+1 equals a magnitude of the frequency division performed by the first integer divider.

6. The multi-stage frequency divider of claim 5 , wherein said duty cycle enhancement circuit is configured to generate an output signal by performing a logical OR of the output signal generated by the second integer divider and the M-cycle delayed version of the output signal generated by the second integer divider.

7. The multi-stage frequency divider of claim 1 , wherein said duty cycle correction circuit is configured to generate a first preliminary output signal by performing a logical OR of a half-cycle delayed version of the intermediate output signal and a 1.5-cycle delayed version of the intermediate output signal.

8. The multi-stage frequency divider of claim 7 , wherein said duty cycle correction circuit is further configured to generate a second preliminary output signal as a one-cycle delayed version of the intermediate output signal.

9. The multi-stage frequency divider of claim 8 , wherein said duty cycle correction circuit is further configured to generate the periodic output signal by multiplexing the first preliminary output signal and the second preliminary output signal using the periodic reference signal as a multiplexer select signal.

10. A multi-stage frequency divider, comprising:
a cascaded arrangement of first and second integer dividers configured to collectively divide a frequency of a periodic reference signal by an integer amount equal to a product of (2N+1) and (2M+1), where N and M are unequal positive integers greater than two; and
a duty cycle enhancement circuit configured to generate a periodic signal having 2MN+N+M cycles of high followed by 2MN+N+M+1 cycles of low or vice versa, where a duration of each cycle is equivalent to a period of the periodic reference signal and said duty cycle enhancement circuit is synchronized to the periodic reference signal; and
a duty cycle correction circuit configured to generate a periodic output signal having a 50% duty cycle from the periodic signal generated by said duty cycle enhancement circuit.

Assignees

• Integrated Device Tech

Inventors

• He Chengming
• Eribes Ruben
• Castile Denny Nathaniel

Classifications

• H03K7/08

  Duration or width modulation {; Duty cycle modulation} · CPC title

• H03K21/10 Primary

  comprising logic circuits · CPC title

• H03K5/1565

  the output pulses having a constant duty cycle · CPC title