Systems and methods for magnetic shielding

Patent metadata

Field	Value
Publication number	US-10326071-B2
Application number	US-201615272268-A
Country	US
Kind code	B2
Filing date	Sep 21, 2016
Priority date	Mar 23, 2010
Publication date	Jun 18, 2019
Grant date	Jun 18, 2019

Abstract

Systems and methods for magnetic shielding are described. A magnetic shield formed of a material having a high magnetic permeability may be degaussed using a toroidal degaussing coil. The toroidal degaussing coil may enclose at least a portion of the shield. Magnetic field gradients may be actively compensated using multiple magnetic field sensors and local compensation coils. Trapped fluxons may be removed by an application of Lorentz force wherein an electrical current is passed through a superconducting plane.

First claim

The invention claimed is:

1. A superconducting chip comprising:
a plurality of superconducting devices;
a superconducting plane positioned above the plurality of superconducting devices;
a first current lead electrically coupled to the superconducting plane;
a second current lead electrically coupled to the superconducting plane; and
a fluxon barrier carried on the superconducting plane, wherein the fluxon barrier is positioned adjacent to an edge of the superconducting plane and extends substantially parallel thereto, and wherein the fluxon barrier comprises at least a first strip of superconducting material.

2. The superconducting chip of claim 1 wherein the fluxon barrier comprises at least a second strip of superconducting material that is stacked on top of the first strip of superconducting material.

3. The superconducting chip of claim 1 wherein the superconducting plane is a superconducting ground plane coupled to a ground.

4. The superconducting chip of claim 1 wherein the second current lead is spaced from the first current lead.

5. The superconducting chip of claim 4 wherein a current that exceeds a critical current of the superconducting plane is supplied via the first and the second current leads.

6. The superconducting chip of claim 5 wherein in response to the supply of the current that exceeds the critical current of the superconducting plane, a Lorentz force expels fluxons in a first direction, the first direction toward a first side of an imaginary line that extends between the first and the second current leads.

7. The superconducting chip of claim 6 , further comprising:
a fluxon barrier carried on the superconducting plane, the fluxon barrier positioned on a second side of the imaginary line that extends between the first and the second current leads, the second side opposed across the imaginary line from the first side of the imaginary line.

8. The superconducting chip of claim 7 wherein the fluxon barrier extends substantially parallel to the imaginary line that extends between the first and the second current leads.

9. The superconducting chip of claim 7 wherein the fluxon barrier comprises a strip of a material that becomes superconductive at a first critical temperature.

10. The superconducting chip of claim 9 wherein the first critical temperature of the strip of a material is higher than a critical temperature of at which the superconducting plane becomes superconductive.

11. The superconducting chip of claim 7 wherein the fluxon barrier comprises a stack of a plurality of strips of a material that superconducts at a critical temperature.

12. The superconducting chip of claim 1 wherein the superconducting plane is at or below a critical temperature at which the superconducting devices superconduct.

13. The superconducting chip of claim 12 wherein, while the superconducting plane is at or below the critical temperature, a current that exceeds a critical current of the superconducting plane is supplied via the first and the second current leads.

14. The superconducting chip of claim 12 wherein, while the superconducting plane approaches and reaches the critical temperature, a current that exceeds a critical current of the superconducting plane is supplied via the first and the second current leads.

15. The superconducting chip of claim 1 wherein a critical temperature at which the superconducting plane begins to superconduct is higher than a critical temperature at which the superconducting devices begin to superconductive.

16. The superconducting chip of claim 1 wherein the first and the second current leads are located at diagonally opposite corners of the superconducting plane.

17. The superconducting chip of claim 1 wherein the superconducting plane is in addition to an existing superconductive plane.

18. The superconducting chip of claim 1 wherein the superconducting devices include a plurality of qubits.

Assignees

• D Wave Systems Inc

Inventors

• Uchaykin Sergey V

Classifications

• H01L39/02 Primary

  Electricity · mapped topic

• H01L27/18

  Electricity · mapped topic

• H01L39/04

  Electricity · mapped topic

• H01F13/006 Primary

  Methods and devices for demagnetising of magnetic bodies, e.g. workpieces, sheet material (for erasing of information on magnetic record carriers G11B5/00) · CPC title

• G05F7/00

  Regulating magnetic variables · CPC title