Burst-tolerant decision feedback equalization

Patent metadata

Field	Value
Publication number	US-10320591-B2
Application number	US-201615570703-A
Country	US
Kind code	B2
Filing date	Jul 22, 2016
Priority date	Jul 28, 2015
Publication date	Jun 11, 2019
Grant date	Jun 11, 2019

Abstract

A first sequence of data bits is shifted into storage elements of a signal receiver during a first sequence of bit-time intervals, and a memory access command indicates that a second sequence of data bits is to be received within the signal receiver during a second sequence of bit-time intervals. Contents of the shift-register storage elements are conditionally overwritten with a predetermined set of seed bits, depending on whether one or more bit-time intervals will transpire between the first and second sequences of bit-time intervals. Equalization signals generated based, at least in part, on contents of the shift-register storage elements are used to adjust respective signal levels representative of one or more bits of the second sequence of data bits.

First claim

What is claimed is:

1. A method of operation within an integrated circuit device, the method comprising:
shifting a first sequence of data bits into storage elements of a shift register during a first sequence of bit-time intervals;
receiving a memory access command indicating that a second sequence of data bits is to be received within the integrated circuit device via an external data signaling path during a second sequence of bit-time intervals;
determining, based at least in part on a temporal offset between the memory access command and a preceding memory access command, whether one or more bit-time intervals will transpire between the first and second sequences of bit-time intervals;
overwriting contents of the shift-register storage elements with a predetermined set of seed bits if one or more bit-time intervals will transpire between the first and second sequences of bit-time intervals;
generating a plurality of equalization signals based, at least in part, on contents of the shift-register storage elements; and
adjusting respective signal levels representative of one or more bits of the second sequence of data bits based on the plurality of equalization signals.

2. The method of claim 1 wherein the preceding memory access command indicates that the first sequence of data bits was received via the external data signaling path during the first sequence of bit-time intervals and wherein shifting the first sequence of data bits into the shift-register storage elements comprises receiving the first sequence of data bits via the external data signaling path.

3. The method of claim 1 wherein receiving the memory access command indicating that the second sequence of data bits is to be received via the external data signaling path comprises receiving a memory write command via an external command signaling path, the memory write command additionally indicating that the second sequence of data bits comprises write data bits to be stored in a core storage array of the integrated circuit device.

4. The method of claim 1 wherein receiving the memory access command indicating that the second sequence of data bits is to be received via the external data signaling path comprises receiving a memory read command from a command queue of the integrated circuit device, the memory read command additionally indicating that the second sequence of data bits comprises read data bits transmitted via the external data signaling path by an integrated-circuit memory component.

5. The method of claim 1 wherein determining, based at least in part on the temporal offset between the memory access command and the preceding memory access command, whether one or more bit-time intervals will transpire between the first and second sequences of bit-time intervals comprises measuring the temporal offset between the memory access command and the preceding memory access command.

6. The method of claim 5 wherein measuring the temporal offset between the memory access command and the preceding memory access command comprises counting transitions of a timing signal between receipt of the memory access command and the preceding memory access command.

7. The method of claim 1 wherein determining, based at least in part on the temporal offset between the memory access command and the preceding memory access command, whether one or more bit-time intervals will transpire between the first and second sequences of time intervals comprises determining whether one or more bit-time intervals will transpire between the first and second sequences of bit-time intervals based, at least in part, on the temporal offset, burst length information conveyed in the preceding memory access command, and a nominal latency between receipt of the memory access command and receipt of the second sequence of data bits.

8. The method of claim 1 further comprising receiving a data strobe signal via an external strobe signal line and shifting the second sequence of bits into the shift-register storage elements in response to transitions of the data strobe signal.

9. The method of claim 8 wherein overwriting contents of the shift-register storage elements with the predetermined set of seed bits if one or more bit-time intervals will transpire between the first and second sequences of bits comprises loading the seed bits into the shift-register storage elements during the interval between first and second bit sequences.

10. The method of claim 1 wherein generating the plurality of equalization signals based, at least in part, on contents of the shift-register storage elements comprises multiplying individual bits stored within the shift-register storage elements with respective coefficient values stored within a programmable register.

11. The method of claim 10 further comprising switchably selecting each of a plurality of different coefficient values to be multiplied with contents of the shift-register storage elements in respective bit-time intervals.

12. An integrated circuit device comprising:
receiver circuitry having storage elements and circuitry to shift a first sequence of data bits into the storage elements during a first sequence of bit-time intervals;
control circuitry to:
receive a memory access command indicating that a second sequence of data bits is to be received via an external data signaling path during a second sequence of bit-time intervals;
determine, based at least in part on a temporal offset between the memory access command and a preceding memory access command, whether one or more bit-time intervals will transpire between the first and second sequences of bit-time intervals; and
overwrite contents of the storage elements with a predetermined set of seed bits if one or more bit-time intervals will transpire between the first and second sequences of bit-time intervals; and

equalizer circuitry to generate a plurality of equalization signals based, at least in part, on contents of the storage elements and to adjust respective signal levels representative of one or more bits of the second sequence of data bits based on the plurality of equalization signals.

13. The integrated circuit device of claim 12 wherein the preceding memory access command indicates that the first sequence of data bits was received via the external data signaling path during the first sequence of bit-time intervals and the receiver circuitry to shift the first sequence of data bits into the storage elements comprises circuitry to receive the first sequence of data bits via the external data signaling path.

14. The integrated circuit device of claim 12 further comprising a core storage array and wherein the control circuitry to receive the memory access command indicating that the second sequence of data bits is to be received via the external data signaling path comprises circuitry to receive a memory write command via an external command signaling path, the memory write command additionally indicating that the second sequence of data bits comprises write data bits to be stored in the core storage array.

15. The integrated circuit device of claim 12 further comprising a command queue to store commands to be output from the integrated circuit device to one or more external memory components, and wherein the control circuitry to receive the memory access command indicating that the second sequence of data bits is to be received via the external data signaling path comprises circuitry to receive a memory read command from the command queue, the memory read command additionally indicating that the second sequence of data bits comprises read data bits transmitted via the external data sig

Assignees

• Rambus Inc

Inventors

• Giovannini Thomas J
• Abhyankar Abhijit

Classifications

• H04L25/03057 Primary

  with a recursive structure (H04L25/03031 takes precedence) · CPC title

• H04L25/03878 Primary

  Line equalisers; line build-out devices · CPC title

• G11C19/00

  Digital stores in which the information is moved stepwise, e.g. shift registers · CPC title

• G06F3/0644

  Management of space entities, e.g. partitions, extents, pools · CPC title

• H04L25/03146 Primary

  with a recursive structure (H04L25/03127 takes precedence) · CPC title