Memory components and controllers that calibrate multiphase synchronous timing references

Patent metadata

Field	Value
Publication number	US-9412428-B2
Application number	US-201214003722-A
Country	US
Kind code	B2
Filing date	Mar 21, 2012
Priority date	Apr 22, 2011
Publication date	Aug 9, 2016
Grant date	Aug 9, 2016

Abstract

A first timing reference signal and a second timing reference signal are sent to a memory device. The second timing reference signal has approximately a quadrature phase relationship with respect to the first timing reference signal. A plurality of serial data patterns are received from the memory device. The transitions of the first timing reference and the second timing reference determining when transitions occur between the bits of the plurality of data patterns. Timing indicators associated with when received transitions occur between the bits of the plurality of data patterns are received from the memory device. The timing indicators are each measured using a single sampler. Based on the timing indicators, a first duty cycle adjustment for the first timing reference signal, a second duty cycle adjustment for the second timing reference signal, and a quadrature phase adjustment are determined and applied.

First claim

What is claimed is:

1. A memory controller, comprising:
a first circuit to send a first timing reference signal to a memory device;
a second circuit to send a second timing reference signal to the memory device, the second timing reference signal to have a quadrature phase relationship with respect to the first timing reference signal, the memory device to send a plurality of calibration bit patterns synchronously with respect to the first timing reference signal and the second timing reference signal;
a receiver circuit to sample the plurality of calibration bit patterns over a range of receive timings, the sampling of the plurality of calibration bit patterns over the range of receive timings resolving a plurality of timing indicators associated with when transitions between bits of the plurality of calibration bit patterns are received; and,
a timing adjustment circuit to adjust, based on the plurality of timing indicators, a duty cycle of the first timing reference, a duty cycle of the second timing reference, and a quadrature phase adjustment between the first timing reference and the second timing reference.

2. The memory controller of claim 1 , further comprising:
a third circuit to generate an internal timing reference signal, the internal timing reference signal variable to cause the receive circuit to sample the plurality of calibration bit patterns over the range of receive timings.

3. The memory controller of claim 1 , wherein the plurality of timing indicators comprises a first timing indicator and a second timing indicator, a first duty cycle of the first timing reference being indicated by a first difference between the first timing indicator and the second timing indicator.

4. The memory controller of claim 3 , wherein, based on the first difference, the timing adjustment circuit is controlled to adjust the duty cycle of the first timing reference.

5. The memory controller of claim 3 wherein the plurality of timing indicators further comprise a third timing indicator, a first quadrature phase being indicated by a second difference between the first timing indicator and the third timing indicator.

6. The memory controller of claim 5 , wherein, based on the second difference, the timing adjustment circuit is controlled to make the quadrature phase adjustment.

7. The memory controller of claim 2 wherein the third circuit is to generate the internal timing reference signal from a second internal timing reference signal input to the third circuit, a delay from the second internal timing reference signal to the internal timing reference signal to be digitally controlled by the third circuit to cause the receive circuit to sample the plurality of calibration bit patterns over the range of receive timings.

8. A method of calibrating, comprising:
sending a first timing reference signal and a second timing reference signal to a memory device, the second timing reference signal to have approximately a quadrature phase relationship with respect to the first timing reference signal;
receiving, from the memory device, a plurality of serial data patterns, the transitions of the first timing reference and the second timing reference determining when transitions occur between the bits of the plurality of data patterns;
resolving information associated with when received transitions occur between the bits of the plurality of data patterns, the resolved information measured using single samplers; and,
based on the resolved information, determining a first duty cycle adjustment for the first timing reference signal, a second duty cycle adjustment for the second timing reference signal, and a quadrature phase adjustment between the first timing reference signal and the second timing reference signal.

9. The method of claim 8 , wherein the single samplers are controlled by an internal timing reference signal received from a single controllable timing reference signal generator.

10. The method of claim 8 , wherein the resolved information comprises a first timing indicator and a second timing indicator, the quadrature phase adjustment being based on a first difference between the first timing indicator and the second timing indicator.

11. The method of claim 10 , wherein the resolved information further comprise a third timing indicator, the first duty cycle adjustment for the first timing reference signal being based on a second difference between the first timing indicator and the third timing indicator.

12. The method of claim 8 , wherein each of the plurality of data patterns is associated with a different transition of the first timing reference signal and the second timing reference signal.

13. The method of claim 8 , wherein each one of the plurality of data patterns is used to determine a single one of the plurality of timing indicators.

14. The method of claim 9 , further comprising:
sweeping the internal timing reference signal over a range of timings in order to determine at least a portion of the resolved information associated with when received transitions occur between the bits of the plurality of data patterns.

15. A memory device, comprising:
a first circuit to receive a first timing reference signal sent by a memory controller;
a second circuit to receive a second timing reference signal sent by the memory controller, the second timing reference signal to have a quadrature phase relationship with respect to the first timing reference signal;
a transmitter circuit to send a plurality of calibration bit patterns over a single line synchronously with respect to the first timing reference signal and the second timing reference signal, the memory controller to sample the plurality of calibration bit patterns over a range of receive timings, the sampling of the plurality of calibration bit patterns over the range of receive timings determining a plurality of timing indicators associated with when transitions between bits of the plurality of calibration bit patterns are received by the memory controller, the memory controller to adjust, based on the plurality of timing indicators, a duty cycle of the first timing reference, a duty cycle of the second timing reference, and a quadrature phase adjustment.

16. The memory device of claim 15 , further comprising:
a third circuit to supply the plurality of calibration bit patterns to the transmitter circuit.

17. The memory device of claim 15 , wherein the plurality of timing indicators comprises a first timing indicator and a second timing indicator, a first duty cycle of the first timing reference being indicated by a first difference between the first timing indicator and the second timing indicator.

18. The memory device of claim 17 , wherein, based on the first difference, the memory controller is to adjust the duty cycle of the first timing reference.

19. The memory device of claim 17 wherein the plurality of timing indicators further comprise a third timing indicator, a first quadrature phase being indicated by a second difference between the first timing indicator and the third timing indicator.

20. The memory device of claim 19 , wherein, based on the second difference, the memory controller is to make the quadrature phase adjustment.

Assignees

• Giovannini Thomas
• Best Scott
• Luo Lei
• Shaeffer Ian
• Rambus Inc

Inventors

• Giovannini Thomas
• Best Scott
• Luo Lei
• Shaeffer Ian

Classifications

• G11C29/50012

  of timing · CPC title

• G11C7/222 Primary

  Clock generating, synchronizing or distributing circuits within memory device · CPC title

• G11C29/023

  in clock generator or timing circuitry · CPC title

• G11C7/227 Primary

  Timing of memory operations based on dummy memory elements or replica circuits · CPC title

• G11C29/028

  with adaption or trimming of parameters · CPC title