Self-aligned gate edge and local interconnect and method to fabricate same

Patent metadata

Field	Value
Publication number	US-10319812-B2
Application number	US-201715789315-A
Country	US
Kind code	B2
Filing date	Oct 20, 2017
Priority date	Dec 19, 2013
Publication date	Jun 11, 2019
Grant date	Jun 11, 2019

Abstract

Self-aligned gate edge and local interconnect structures and methods of fabricating self-aligned gate edge and local interconnect structures are described. In an example, a semiconductor structure includes a semiconductor fin disposed above a substrate and having a length in a first direction. A gate structure is disposed over the semiconductor fin, the gate structure having a first end opposite a second end in a second direction, orthogonal to the first direction. A pair of gate edge isolation structures is centered with the semiconductor fin. A first of the pair of gate edge isolation structures is disposed directly adjacent to the first end of the gate structure, and a second of the pair of gate edge isolation structures is disposed directly adjacent to the second end of the gate structure.

First claim

What is claimed is:

1. An integrated circuit structure, comprising:
a first fin having a longest dimension along a first direction;
a second fin having a longest dimension along the first direction;
a first gate structure over the first fin, the first gate structure having a longest dimension along a second direction, the second direction orthogonal to the first direction;
a second gate structure over the second fin, the second gate structure having a longest dimension along the second direction, the second gate structure discontinuous with the first gate structure along the second direction, and the second gate structure having an edge facing an edge of the first gate structure along the second direction;
a gate edge isolation structure between and in contact with the edge of the first gate structure and the edge of the second gate structure along the second direction, the gate edge isolation structure having a length along the first direction greater than a length of the first gate structure and the second gate structure along the first direction; and
a dielectric material laterally adjacent to and in contact with the gate edge isolation structure, and the dielectric material having a composition different than a composition of the gate edge isolation structure.

2. The integrated circuit structure of claim 1 , wherein the first gate structure comprises a first gate dielectric layer and a first gate electrode, and wherein the second gate structure comprises a second gate dielectric layer and a second gate electrode.

3. The integrated circuit structure of claim 2 , wherein the gate edge isolation structure is in contact with a gate dielectric layer of the first gate structure and with a gate dielectric layer of the second gate structure.

4. The integrated circuit structure of claim 3 , wherein the gate edge isolation structure is in contact with a metal gate electrode layer of the first gate structure and with a metal gate electrode layer of the second gate structure.

5. The integrated circuit structure of claim 2 , wherein the gate dielectric layer of the first gate structure comprises a high-k dielectric material, and wherein the gate dielectric layer of the second gate structure comprises a high-k dielectric material.

6. The integrated circuit structure of claim 1 , wherein the gate edge isolation structure has a height greater than a height of the first gate structure and greater than a height of the second gate structure.

7. The integrated circuit structure of claim 6 , further comprising:
a local interconnect disposed over a portion of the first gate structure, over a portion of the gate edge isolation structure, and over a portion of the second gate structure.

8. The integrated circuit structure of claim 7 , wherein the local interconnect electrically couples the first gate structure to the second gate structure.

9. The integrated circuit structure of claim 8 , further comprising:
a gate contact on a portion of the local interconnect over the first gate structure, but not on a portion of the local interconnect over the second gate structure.

10. The integrated circuit structure of claim 1 , wherein the gate edge isolation structure comprises silicon and nitrogen.

11. A method of fabricating and integrated circuit structure, the method comprising:
forming a first fin having a longest dimension along a first direction;
forming a second fin having a longest dimension along the first direction;
forming a first gate structure over the first fin, the first gate structure having a longest dimension along a second direction, the second direction orthogonal to the first direction;
forming a second gate structure over the second fin, the second gate structure having a longest dimension along the second direction, the second gate structure discontinuous with the first gate structure along the second direction, and the second gate structure having an edge facing an edge of the first gate structure along the second direction;
forming a gate edge isolation structure between and in contact with the edge of the first gate structure and the edge of the second gate structure along the second direction, the gate edge isolation structure having a length along the first direction greater than a length of the first gate structure and the second gate structure along the first direction; and
forming a dielectric material laterally adjacent to and in contact with the gate edge isolation structure, and the dielectric material having a composition different than a composition of the gate edge isolation structure.

12. The method of claim 11 , wherein the first gate structure comprises a first gate dielectric layer and a first gate electrode, and wherein the second gate structure comprises a second gate dielectric layer and a second gate electrode.

13. The method of claim 12 , wherein the gate edge isolation structure is in contact with a gate dielectric layer of the first gate structure and with a gate dielectric layer of the second gate structure.

14. The method of claim 13 , wherein the gate edge isolation structure is in contact with a metal gate electrode layer of the first gate structure and with a metal gate electrode layer of the second gate structure.

15. The method of claim 12 , wherein the gate dielectric layer of the first gate structure comprises a high-k dielectric material, and wherein the gate dielectric layer of the second gate structure comprises a high-k dielectric material.

16. The method of claim 11 , wherein the gate edge isolation structure has a height greater than a height of the first gate structure and greater than a height of the second gate structure.

17. The method of claim 16 , further comprising:
forming a local interconnect disposed over a portion of the first gate structure, over a portion of the gate edge isolation structure, and over a portion of the second gate structure.

18. The method of claim 17 , wherein the local interconnect electrically couples the first gate structure to the second gate structure.

19. The method of claim 18 , further comprising:
forming a gate contact on a portion of the local interconnect over the first gate structure, but not on a portion of the local interconnect over the second gate structure.

20. The method of claim 11 , wherein the gate edge isolation structure comprises silicon and nitrogen.

21. A method of fabricating an integrated circuit structure, the method comprising:
forming a first fin comprising silicon, the first fin having a longest dimension along a first direction;
forming a second fin comprising silicon, the second fin having a longest dimension along the first direction;
forming an isolation material between the first fin and the second fin;
forming a first gate structure over the first fin, the first gate structure having a longest dimension along a second direction, the second direction orthogonal to the first direction, wherein the first gate structure comprises a first gate dielectric layer and a first gate electrode;
forming a second gate structure over the second fin, the second gate structure having a longest dimension along the second direction, the second gate structure discontinuous with the first gate structure along the second direction, and the second gate structure having an edge facing an edge of the first gate structure along the second direction, wherein the second gate structure comprises a second gate dielectric layer and a second gate electrode;
forming a gate edge isolation structure between and

Assignees

• Intel Corp

Inventors

• Webb Milton Clair
• Bohr Mark
• Ghani Tahir
• Liao Szuya S

Classifications

• H10W20/0698

  Local interconnections · CPC title

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H01L21/823821

  Electricity · mapped topic

• H01L29/66545

  Electricity · mapped topic

• H01L29/785

  Electricity · mapped topic