Array substrate, display panel, and display apparatus

Patent metadata

Field	Value
Publication number	US-10319747-B2
Application number	US-201615508102-A
Country	US
Kind code	B2
Filing date	Jul 1, 2016
Priority date	Jan 14, 2016
Publication date	Jun 11, 2019
Grant date	Jun 11, 2019

Abstract

An array substrate includes: a plurality of pixels including sub-pixels forming a matrix, each sub-pixel including a pair of sub-pixel portions; a plurality of data lines; a plurality of gate lines intersecting with the plurality of data lines; and a plurality of pairs of transistors configured to control the plurality of pairs of sub-pixel portions; wherein: each pair of transistors are disposed adjacent to an intersection between a gate line and a data line, across at least one of the gate line or the data line, and are configured to control a pair of sub-pixel portions in neighboring rows or columns of sub-pixel portions.

First claim

The invention claimed is:

1. An array substrate, comprising:
a plurality of pixels including sub-pixels forming a matrix, each sub-pixel including a pair of sub-pixel portions of domains of the each sub-pixel;
a plurality of data lines;
a plurality of gate lines intersecting with the plurality of data lines; and
a plurality of pairs of transistors configured to control the plurality of pairs of sub-pixel portions;
wherein:
each pair of transistors are disposed adjacent to an intersection between a gate line and a data line, across at least one of the gate line or the data line, and are configured to control a pair of sub-pixel portions in neighboring rows or columns of sub-pixel portions;
each of the plurality of sub-pixels comprises two pixel electrodes corresponding to the pair of sub-pixel portions;
the pair of sub-pixel portions form a dual-domain configuration;
the two pixel electrodes are insulated from one another, and have opposite domain tilt directions;
the plurality of data lines alternate with the plurality of columns of sub-pixel portions such that one data line is arranged between two neighboring columns of sub-pixel portions; and
one gate line is arranged between two rows of sub-pixel portions.

2. The array substrate of claim 1 , wherein the pair of transistors are disposed across both the gate line and the data line.

3. The array substrate of claim 2 , wherein for each pair of transistors,
gate electrodes of the pair of transistors are integrated and are coupled with the gate line;
source electrodes of the pair of transistors are disposed over the data line; and
drain electrodes of the pair of transistors are respectively disposed at two sides of the data line.

4. The array substrate of claim 3 , wherein the drain electrodes of each pair of transistors are respectively coupled with two pixel electrodes diagonally disposed in two neighboring columns of sub-pixel portions.

5. The array substrate of claim 4 , wherein the two pixel electrodes diagonally located in two neighboring columns of sub-pixel portions comprise a first pixel electrode on a first row and on an even-numbered column, and a second pixel electrode on a second row and on an odd-numbered column.

6. The array substrate of claim 4 , wherein the two pixel electrodes diagonally located in two neighboring pixel units on a same row of pixel units comprises a first pixel electrode on a first row and on an odd-numbered column, and a second pixel electrode on a second row and on an even-numbered column.

7. The array substrate of claim 1 , wherein the pair of transistors are disposed across the gate line and at one side of the data line.

8. The array substrate of claim 7 , wherein for each pair of transistors,
gate electrodes of the pair of transistors are integrated and are coupled with the gate line;
source electrodes of the pair of transistors both are disposed over the data line; and
drain electrodes of the pair of transistors are respectively disposed at two sides of the gate line and are integrated.

9. The array substrate of claim 8 , wherein the drain electrodes of each pair of transistors are respectively coupled with two pixel electrodes in a same column.

10. The array substrate of claim 1 , wherein the pair of transistors are disposed across the data line and at one side of the gate line.

11. The array substrate of claim 10 , wherein each pair of transistors are configured to control two pixel electrodes located on the one side of the gate line in two neighboring sub-pixel portions on a same row.

12. The array substrate of claim 1 , wherein the plurality of data lines are parallel to each other and the plurality of gate lines are parallel to each other.

13. The array substrate of claim 1 , further comprising a plurality of common electrode lines disposed in rows and alternating with the plurality of gate lines.

14. The array substrate of claim 13 , wherein the plurality of common electrode lines are parallel to each other.

15. The array substrate of claim 1 , wherein each pair of transistors are integrally formed.

16. The array substrate of claim 1 , wherein the transistors are thin-film transistors (TFTs).

17. The array substrate of claim 16 , wherein each TFT further comprises an active layer disposed between a gate electrode layer and a layer of source electrode and drain electrode.

18. A display panel, comprising an array substrate including:
a plurality of pixels including sub-pixels forming a matrix, each sub-pixel including a pair of sub-pixel portions of domains of the each sub-pixel;
a plurality of data lines;
a plurality of gate lines intersecting with the plurality of data lines; and
a plurality of pairs of transistors configured to control the plurality of pairs of sub-pixel portions;
wherein:
each pair of transistors are disposed adjacent to an intersection between a gate line and a data line, across at least one of the gate line or the data line, and are configured to control a pair of sub-pixel portions in neighboring rows or columns of sub-pixel portions;
each of the plurality of sub-pixels comprises two pixel electrodes corresponding to the pair of sub-pixel portions;
the pair of sub-pixel portions form a dual-domain configuration;
the two pixel electrodes are insulated from one another, and have opposite domain tilt directions;
the plurality of data lines alternate with the plurality of columns of sub-pixel portions such that one data line is arranged between two neighboring columns of sub-pixel portions; and

one gate line is arranged between two rows of sub-pixel portions.

19. A display apparatus, comprising a display panel having an array substrate, the array substrate comprising:
a plurality of pixels including sub-pixels forming a matrix, each sub-pixel including a pair of sub-pixel portions of domains of the each sub-pixel;
a plurality of data lines;
a plurality of gate lines intersecting with the plurality of data lines; and
a plurality of pairs of transistors configured to control the plurality of pairs of sub-pixel portions;
wherein:
each pair of transistors are disposed adjacent to an intersection between a gate line and a data line, across at least one of the gate line or the data line, and are configured to control a pair of sub-pixel portions in neighboring rows or columns of sub-pixel portions;
each of the plurality of sub-pixels comprises two pixel electrodes corresponding to the pair of sub-pixel portions;
the pair of sub-pixel portions form a dual-domain configuration;
the two pixel electrodes are insulated from one another, and have opposite domain tilt directions;
the plurality of data lines alternate with the plurality of columns of sub-pixel portions such that one data line is arranged between two neighboring columns of sub-pixel portions; and

one gate line is arranged between two rows of sub-pixel portions.

Assignees

• Boe Technology Group Co Ltd
• Hefei Boe Optoelectronics Tech

Inventors

• Chen Chuanbao
• Yang Jie
• Yin Xiaobin

Classifications

• G02F2201/121

  common or background · CPC title

• G02F1/136286 Primary

  Wiring, e.g. gate line, drain line · CPC title

• H01L29/42384

  Electricity · mapped topic

• G02F1/134309

  characterised by their geometrical arrangement · CPC title

• H01L27/124 Primary

  Electricity · mapped topic