Pixel structure, array substrate and display device

Patent metadata

Field	Value
Publication number	US-2016357073-A1
Application number	US-201615096895-A
Country	US
Kind code	A1
Filing date	Apr 12, 2016
Priority date	Jun 3, 2015
Publication date	Dec 8, 2016
Grant date	—

Abstract

A pixel structure according to embodiments of the present disclosure may include a plurality of sub-pixel units driven by a same gate line and a same data line. Each of the sub-pixel units may consist of two or more sub-pixels, and be divided into N display regions. In a power-on state, an N-domain display may be implemented by the sub-pixel unit due to different electric fields generated by different display regions respectively. Technical solutions of the present disclosure can improve chromatic aberration phenomenon of a LCD device with transmittance of the LCD device being guaranteed.

First claim

What is claimed is:

1 . A pixel structure, comprising:
a plurality of sub-pixel units driven by a same gate line and a same data line, wherein each of the sub-pixel units consists of two or more sub-pixels, and is divided into N display regions; and wherein in a power-on state, an N-domain display is implemented by the sub-pixel unit due to different electric fields generated by different display regions respectively.

2 . The pixel structure according to claim 1 , wherein each of the sub-pixel units is divided into four display regions.

3 . The pixel structure according to claim 2 , wherein each of the sub-pixel units comprises two sub-pixels driven by the same gate line and the same data line, each sub-pixel being divided into two display regions.

4 . The pixel structure according to claim 3 , wherein each of the sub-pixel units consists of a first sub-pixel and a second sub-pixel distributed in a substantially parallel direction along the gate line, the sub-pixel unit comprising a first thin film transistor (TFT) which drives the first sub-pixel for display and a second TFT which drives the second sub-pixel for display, a gate electrode of the first TFT being connected to a gate electrode of the second TFT, a source electrode of the first TFT being connected to a source electrode of the second TFT; in a substantially parallel direction along the data line, the first sub-pixel is divided into a first region and a second region whose areas are substantially identical, and the second sub-pixel is divided into a third region and a fourth region whose areas are substantially identical; and strip pixel electrodes of the first region and the second region are arranged symmetrically, and strip pixel electrodes of the third region and the fourth region are arranged symmetrically;
wherein inclination angles of the strip pixel electrodes of the first region and the third region are substantially identical, width-length ratios of channels of the first TFT and the second TFT are substantially identical, and areas of the first region and the third region are different; or inclination angles of the strip pixel electrodes of the first region and the third region are substantially identical, width-length ratios of channels of the first TFT and the second TFT are different, and areas of the first region and the third region are substantially identical; or inclination angles of the strip pixel electrodes of the first region and the third region are different, width-length ratios of channels of the first TFT and the second TFT are substantially identical, and areas of the first region and the third region are substantially identical.

5 . The pixel structure according to claim 3 , wherein each of the sub-pixel units consists of a first sub-pixel and a second sub-pixel distributed in a substantially parallel direction along the data line, the sub-pixel unit comprising a first thin film transistor (TFT) which drives the first sub-pixel for display and a second TFT which drives the second sub-pixel for display, a gate electrode of the first TFT being connected to a gale electrode of the second TFT, a source electrode of the first TFT being connected to a source electrode of the second TFT; in a substantially parallel direction along the gate line, the first sub-pixel is divided into a first region and a second region whose areas are substantially identical, and the second sub-pixel is divided into a third region and a fourth region whose areas are substantially identical; and strip pixel electrodes of the first region and the second region are arranged symmetrically, and strip pixel electrodes of the third region and the fourth region are arranged symmetrically;
wherein inclination angles of the strip pixel electrodes of the first region and the third region are substantially identical, width-length ratios of channels of the first TFT and the second TFT are substantially identical, and areas of the first region and the third region are different; or inclination angles of the strip pixel electrodes of the first region and the third region are substantially identical, width-length ratios of channels of the first TFT and the second TFT are different, and areas of the first region and the third region are substantially identical; or inclination angles of the strip pixel electrodes of the first region and the third region are different, width-length ratios of channels of the first TFT and the second TFT are substantially identical, and areas of the first region and the third region are substantially identical.

6 . The pixel structure according to claim 2 , wherein each of the sub-pixel units comprises four sub-pixels driven by the same gate line and the same data line, each sub-pixel being as one display region.

7 . The pixel structure according to claim 6 , wherein each of the sub-pixel units comprises a first sub-pixel and a second sub-pixel whose areas are substantially identical as well as a third sub-pixel and a fourth sub-pixel whose areas are substantially identical, and further comprises a first TFT which drives the first sub-pixel for display, a second TFT which drives the second sub-pixel for display, a third TFT which drives the third sub-pixel for display, a fourth TFT which drives the fourth sub-pixel for display, gate electrodes of the first TFT, the second TFT, the third TFT and the fourth TFT being connected, source electrodes of the first TFT, the second TFT, the third TFT and the fourth TFT being connected; in a substantially parallel direction along the gate line, strip pixel electrodes of the first sub-pixel and the second sub-pixel are arranged symmetrically, strip pixel electrodes of the third sub-pixel and the fourth sub-pixel are arranged symmetrically, width-length ratios of channels of the first TFT and the second TFT are substantially identical, and width-length ratios of channels of the third TFT and the fourth TFT are substantially identical;
wherein inclination angles of the strip pixel electrodes of the first sub-pixel and the third sub-pixel are substantially identical, width-length ratios of channels of the first TFT and the third TFT are substantially identical, and areas of the first sub-pixel and the third sub-pixel are different; or inclination angles of the strip pixel electrodes of the first sub-pixel and the third sub-pixel are substantially identical, width-length ratios of channels of the first TFT and the third TFT are different, and areas of the first sub-pixel and the third sub-pixel are substantially identical; or inclination angles of the strip pixel electrodes of the first sub-pixel and the third sub-pixel are different, width-length ratios of channels of the first TFT and the third TFT are substantially identical, and areas of the first sub-pixel and the third sub-pixel are substantially identical.

8 . The pixel structure according to claim 6 , wherein each of the sub-pixel units comprises a first sub-pixel and a second sub-pixel whose areas are substantially identical as well as a third sub-pixel and a fourth sub-pixel whose areas are substantially identical, and further comprises a first TFT which drives the first sub-pixel for display, a second TFT which drives the second sub-pixel for display, a third TFT which drives the third sub-pixel for display, a fourth TFT which drives the fourth sub-pixel for display, gate electrodes of the first ‘TF’T, the second TFT, the third TFT and the fourth TFT being connected, source electrodes of the first TFT, the second TFT, the third TFT and the fourth TFT being connected; in a substantially parallel direction along the data line, strip pixel electrodes of the first sub-pixel and the second sub-pixel are arranged symmetrically, strip pixel electrodes of the third sub-pixel and the

Assignees

• Boe Technology Group Co Ltd
• Hefei Xinsheng Optoelectronics Technology Co Ltd

Inventors

• Zhang Xinxia
• Lv Fengzhen
• Guo Xiao
• Xiang Kang
• Wang Chen
• Lv Kui

Classifications

• G02F2201/123

  pixel · CPC title

• G02F1/13624

  having more than one switching element per pixel · CPC title

• G02F1/134309 Primary

  characterised by their geometrical arrangement · CPC title

• G02F1/13306

  Circuit arrangements or driving methods for the control of single liquid crystal cells (G02F1/132, G02F1/133382 take precedence) · CPC title

• G02F1/136286 Primary

  Wiring, e.g. gate line, drain line · CPC title