Array substrate, manufacturing method thereof and display device

Patent metadata

Field	Value
Publication number	US-9728558-B2
Application number	US-201414428515-A
Country	US
Kind code	B2
Filing date	Jun 30, 2014
Priority date	Jan 27, 2014
Publication date	Aug 8, 2017
Grant date	Aug 8, 2017

Abstract

An array substrate, a manufacturing method thereof and a display device are provided; in the array substrate, two adjacent rows of the pixel units ( 200 ) are taken as a group of pixel unit rows; in each group of the pixel unit rows, since the pixel electrodes in two adjacent pixel units ( 200 ) of a same column are all electrically connected with one composite transistor ( 300 ), and the composite transistor ( 300 ) can be turned on or off under the control of different levels of control voltages, to charge the pixel electrodes in two adjacent pixel units ( 200 ) of the same column at different times, each group of the pixel unit row can share a gate line located between the two rows of the pixel units, as compared with the conventional array substrate, the number of the gate lines disposed on the array substrate is reduced by half, so that the aperture ratio of the array substrate can be improved, and the brightness of the display panel can be further improved.

First claim

What is claimed is:

1. An array substrate, comprising a base substrate, and a plurality of pixel units arranged in a matrix, each of which has a pixel electrode, wherein,
with two adjacent rows of the pixel units as a group of pixel unit rows, each group of the pixel unit rows share one gate line located between the two rows of the pixel units, and there is one data line between every two adjacent columns of the pixel units;
in each group of the pixel unit row, pixel electrodes in two adjacent pixel units of a same column are respectively electrically connected with two output terminals of a composite transistor, a control terminal of the composite transistor being electrically connected with the gate line, and an input terminal of the composite transistor being electrically connected with the data line; wherein,
the composite transistor respectively opens conductive paths between the two output terminals and the input terminal under control of different levels of control voltages,
wherein the composite transistor includes a first thin film transistor and a second thin film transistor which are disposed in a stacking manner in a direction perpendicular to the base substrate; one of the first thin film transistor and the second thin film transistor is of top gate type, and the other one is of bottom gate type; and
wherein the first thin film transistor and the second thin film transistor share a gate electrode.

2. The array substrate according to claim 1 , wherein, the composite transistor further includes an active layer of the first thin film transistor and an active layer of the second thin film transistor have opposite doping polarities; wherein,
in each group of the pixel unit rows, a drain electrode of the first thin film transistor is electrically connected with the pixel electrode of the pixel unit located in a first row, a drain electrode of the second thin film transistor is electrically connected with the pixel electrode of the pixel unit located in a second row, a gate electrode of the first thin film transistor and a gate electrode of the second thin film transistor are respectively electrically connected with the gate line, and a source electrode of the first thin film transistor and a source electrode of the second thin film transistor are respectively electrically connected with the data line; the drain electrode of the first thin film transistor and the drain electrode of the second thin film transistor are respectively the two output terminals of the composite transistor, the source electrode of the first thin film transistor and the source electrode of the second thin film transistor are the input terminal of the composite transistor, and the gate electrode of the first thin film transistor and the gate electrode of the second thin film transistor are the control terminal of the composite transistor.

3. The array substrate according to claim 2 , wherein, threshold voltages of the first thin film transistor and the second thin film transistor have opposite polarities.

4. The array substrate according to claim 3 , wherein, the data line and the source electrode of the first thin film transistor are disposed on a same layer, and the source electrode of the second thin film transistor is electrically connected with the data line through a via hole; or
the data line and the source electrode of the second thin film transistor are disposed on a same layer, and the source electrode of the first thin film transistor is electrically connected with the data line through a via hole.

5. The array substrate according to claim 1 , wherein, the first thin film transistor is located between the base substrate and the second thin film transistor; or,
the second thin film transistor is located between the base substrate and the first thin film transistor.

6. The array substrate according to claim 5 , wherein, the first thin film transistor is located between the base substrate and the second thin film transistor, a first light-blocking layer is disposed between the base substrate and the first thin film transistor, and an orthographic projection of the first light-blocking layer on the base substrate covers an orthographic projection of the active layer of the first thin film transistor on the base substrate; or
the second thin film transistor is located between the base substrate and the first thin film transistor, a second light-blocking layer is disposed between the base substrate and the second base substrate, and an orthographic projection of the second light-blocking layer on the base substrate covers an orthographic projection of the active layer of the second thin film transistor on the base substrate.

7. The array substrate according to claim 5 , wherein, a first ohmic contact layer is disposed between the active layer and the source electrode, and between the active layer and the drain electrode of the first thin film transistor; and/or, a second ohmic contact layer is disposed between the active layer and the source electrode, and between the active layer and the drain electrode of the second thin film transistor.

8. A display device, comprising the array substrate according to claim 1 .

9. The array substrate according to claim 1 , wherein, the data line and the source electrode of the first thin film transistor are disposed on a same layer, and the source electrode of the second thin film transistor is electrically connected with the data line through a via hole; or
the data line and the source electrode of the second thin film transistor are disposed on a same layer, and the source electrode of the first thin film transistor is electrically connected with the data line through a via hole.

Assignees

• Boe Technology Group Co Ltd
• Beijing Boe Optoelectronics Tech Co Ltd

Inventors

• Shen Qiyu

Classifications

• G02F1/136286

  Wiring, e.g. gate line, drain line · CPC title

• H01L27/1251

  Electricity · mapped topic

• H01L27/1259

  Electricity · mapped topic

• H01L27/124 Primary

  Electricity · mapped topic

• G02F1/1368

  in which the switching element is a three-electrode device {(G02F1/136277 takes precedence)} · CPC title