Antenna on ceramics for a packaged die

Patent metadata

Field	Value
Publication number	US-10319688-B2
Application number	US-201314361625-A
Country	US
Kind code	B2
Filing date	Dec 9, 2013
Priority date	Dec 9, 2013
Publication date	Jun 11, 2019
Grant date	Jun 11, 2019

Abstract

An antenna is described on ceramics that may be used for a packaged die. In one example, a package has a die, a ceramic substrate over the die, an antenna attached to the ceramic substrate, and conductive leads electrically connecting the antenna to the die.

First claim

What is claimed is:

1. A package comprising:
a die;
a dielectric ceramic substrate over the die, the ceramic substrate having a thickness of at least 10 micrometers, wherein the dielectric ceramic substrate has a first surface facing the die, a second surface facing away from the die, and a sidewall surface connecting the first surface to the second surface;
an antenna formed on the second surface of the ceramic substrate, wherein the antenna is positioned over the die, the antenna being positioned such that the dielectric of the ceramic increases the resonant frequency of the antenna;
a conductive shield layer between the first surface of the ceramic substrate and the die;
conductive leads electrically connecting the antenna to the die; and
a mold compound over the die and completely covering the sidewall surface of the ceramic substrate.

2. The package of claim 1 , wherein the shield layer is formed on the first surface of the ceramic substrate.

3. The package of claim 1 , wherein the conductive leads comprise through-mold vias from the antenna to the die.

4. The package of claim 1 , wherein the shield is grounded through a via to an external connection.

5. The package of claim 1 , further comprising a package substrate attached to the die and wherein at least a portion of the conductive leads are coupled to the die through the package substrate.

6. The package of claim 5 , wherein the conductive leads include routing paths in the package substrate.

7. The package of claim 5 , further comprising a mold compound over the ceramic substrate and the die and wherein the package substrate comprises a redistribution layer on a front side of the die and on the mold compound.

8. The package of claim 1 , wherein the shield layer on the first surface is to isolate the antenna from the die, the package further comprising a conductive trace on a third surface of the ceramic substrate between the first surface and the second surface to electrically connect the antenna to a conductive lead proximate the first surface.

9. The package of claim 1 , further comprising a package cover over the die between the die and the ceramic substrate, wherein the ceramic substrate has conductive pads coupled to the antenna, wherein the ceramic substrate is attached to the package cover using solder balls on the pads, and wherein the conductive leads comprise the pads and the solder balls.

10. The package of claim 9 , wherein the package cover comprises a redistribution layer having connections to a second die.

11. The package of claim 9 , wherein the conductive leads comprise solder-filled vias.

12. The package of claim 1 , wherein the dielectric ceramic substrate has a loss tangent of less than 0.005.

13. A computing system comprising:
a processor;
a user interface; and
a communications chip in a package, the package having a die, a dielectric ceramic substrate over the die, the ceramic substrate being a having a thickness of at least 10 micrometers, wherein the dielectric ceramic substrate has a first surface facing the die, a second surface facing away from the die, and a sidewall surface connecting the first surface to the second surface, an antenna formed on the second surface of the ceramic substrate, the antenna being positioned such that the dielectric of the ceramic increases the resonant frequency of the antenna, a conductive shield layer between the first surface of the ceramic substrate and the die, a mold compound over the die and completely covering the sidewall surface of the ceramic substrate, a redistribution layer formed on a front side of the die and on the mold compound and conductive leads electrically connecting the antenna to the redistribution layer.

14. The computing system of claim 13 , further comprising conductive paths on the ceramic substrate to connect the antenna on the second surface of the substrate to a via connected to the first surface of the substrate.

15. The computing system of claim 13 , further comprising a conductive trace on a third surface of the ceramic substrate between the first surface and the second surface to electrically connect the antenna to the conductive lead proximate the first surface.

16. A method comprising:
forming a dielectric ceramic substrate with a thickness of at least 10micrometers, wherein the dielectric ceramic substrate has a first surface, a second surface, and a sidewall surface connecting the first surface to the second surface;
attaching an antenna to the second surface of the ceramic substrate, the antenna being attached such that the dielectric of the ceramic increases the resonant frequency of the antenna;
applying a conductive shield layer on the first surface of the ceramic substrate;
attaching the ceramic substrate to a die, wherein the first surface of the ceramic substrate is facing the die, and the second surface of the ceramic substrate is facing away from the die;
forming a cover over the die and completely covering the sidewall surface of the ceramic substrate;
forming a redistribution layer over the cover and the die; and
electrically connecting the antenna to the die through the redistribution layer.

17. The method of claim 16 , wherein attaching an antenna comprises depositing conductive lines on a surface of the ceramic substrate.

18. The method of claim 17 , wherein forming a cover comprises applying a mold compound over the ceramic substrate and the die and wherein forming a redistribution layer comprises forming a redistribution layer on a front side of the die and on the mold compound.

Assignees

• Intel Corp

Inventors

• Wolter Andreas
• Maruthamuthu Saravana
• Knudsen Mikael
• Meyer Thorsten
• Seidemann Georg
• Herrero Pablo
• Jaervinen Pauli

Classifications

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W72/874

  On different surfaces · CPC title

• H10W72/877

  Bump connectors and die-attach connectors · CPC title

• H10W70/60

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title