Semiconductor treatment composition and treatment method

Patent metadata

Field	Value
Publication number	US-10319605-B2
Application number	US-201715584168-A
Country	US
Kind code	B2
Filing date	May 2, 2017
Priority date	May 10, 2016
Publication date	Jun 11, 2019
Grant date	Jun 11, 2019

Abstract

A semiconductor treatment composition includes particles having a particle size of 0.1 to 0.3 micrometers in a number of 3×101 to 1.5×103 per mL.

First claim

What is claimed is:

1. A semiconductor treatment composition comprising:
particles having a particle size of 0.1 to 0.3 micrometers in a number of 3×10 1 to 1.5×10 3 per mL,
wherein the particles include at least one particles selected from a group consisting of metal particles and metal oxide particles.

2. The semiconductor treatment composition according to claim 1 , the semiconductor treatment composition being used in a 1 to 500-fold diluted state.

3. The semiconductor treatment composition according to claim 1 , further comprising an organic acid.

4. The semiconductor treatment composition according to claim 1 , further comprising a water-soluble polymer.

5. The semiconductor treatment composition according to claim 4 , wherein the weight average molecular weight (Mw) of the water-soluble polymer is from 1,000 to 1,500,000.

6. The semiconductor treatment composition according to claim 1 , further comprising an amine.

7. The semiconductor treatment composition according to claim 1 , wherein said particles comprise 30 parts by mass or more, based on 100 parts by mass of the total mass of said particles, which have a ratio (Rmax/Rmin) of the major axis (Rmax) to the minor axis (Rmin) of 1.3 or more.

8. The semiconductor treatment composition according to claim 1 , wherein said particles comprise 30 parts by mass or more, based on 100 parts by mass of the total mass of said particles, which have a ratio (Rmax/Rmin) of the major axis (Rmax) to the minor axis (Rmin) of 1.4 to 3.0.

9. A treatment method comprising:
treating a wiring board by using the semiconductor treatment composition according to claim 1 , the wiring board containing a wiring material and a barrier metal material, the wiring material being copper or tungsten, and the barrier metal material being at least one material selected from a group consisting of tantalum, titanium, cobalt, ruthenium, manganese, and compounds thereof.

10. A treatment method comprising:
treating a wiring board that contains tungsten as a wiring material by using the semiconductor treatment composition according to claim 1 , after subjecting the wiring board to chemical mechanical polishing by using a composition that contains iron ions and peroxides.

11. A semiconductor treatment composition comprising:
particles having a particle size of 0.1 to 0.3 micrometers in a number of 3×10 1 to 1.5×10 3 per mL,
wherein the particles include silica particles.

12. The semiconductor treatment composition according to claim 11 , the semiconductor treatment composition being used in a 1 to 500-fold diluted state.

13. The semiconductor treatment composition according to claim 11 , further comprising an organic acid.

14. The semiconductor treatment composition according to claim 11 , further comprising a water-soluble polymer.

15. The semiconductor treatment composition according to claim 14 , wherein the weight average molecular weight (Mw) of the water-soluble polymer is from 1,000 to 1,500,000.

16. The semiconductor treatment composition according to claim 11 , further comprising an amine.

17. The semiconductor treatment composition according to claim 11 , wherein said particles comprise 30 parts by mass or more, based on 100 parts by mass of the total mass of said particles, which have a ratio (Rmax/Rmin) of the major axis (Rmax) to the minor axis (Rmin) of 1.3 or more.

18. The semiconductor treatment composition according to claim 11 , wherein said particles comprise 30 parts by mass or more, based on 100 parts by mass of the total mass of said particles, which have a ratio (Rmax/Rmin) of the major axis (Rmax) to the minor axis (Rmin) of 1.4 to 3.0.

19. A treatment method comprising:
treating a wiring board by using the semiconductor treatment composition according to claim 11 , the wiring board containing a wiring material and a barrier metal material, the wiring material being copper or tungsten, and the barrier metal material being at least one material selected from a group consisting of tantalum, titanium, cobalt, ruthenium, manganese, and compounds thereof.

20. A treatment method comprising:
treating a wiring board that contains tungsten as a wiring material by using the semiconductor treatment composition according to claim 11 , after subjecting the wiring board to chemical mechanical polishing by using a composition that contains iron ions and peroxides.

Assignees

• Jsr Corp

Inventors

• Kamei Yasutaka
• Hayama Takahiro
• Nishiguchi Naoki
• Kamo Satoshi
• Shinoda Tomotaka

Classifications

• H10P70/277

  the processing being a planarisation of conductive layers · CPC title

• H10P52/402

  of semiconductor materials · CPC title

• H10P52/403 Primary

  of conductive or resistive materials · CPC title

• C11D11/0047

  Chemistry & Metallurgy · mapped topic

• C09G1/04

  Aqueous dispersions (C09G1/02 takes precedence) · CPC title